<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/nv.c, branch v6.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-06-01T19:56:49Z</updated>
<entry>
<title>drm/amdgpu: update VCN codec support for Yellow Carp</title>
<updated>2022-06-01T19:56:49Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-05-26T20:34:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=97e50305542f384741a5b45699aba349fe9fca73'/>
<id>urn:sha1:97e50305542f384741a5b45699aba349fe9fca73</id>
<content type='text'>
Supports AV1.  Mesa already has support for this and
doesn't rely on the kernel caps for yellow carp, so
this was already working from an application perspective.

Fixes: 554398174d98 ("amdgpu/nv.c - Added video codec support for Yellow Carp")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2002
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: simplify nv and soc21 read_register functions</title>
<updated>2022-05-06T20:56:57Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-05-05T03:24:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bf1781e17f30a594f959671af59a253e9313a9b9'/>
<id>urn:sha1:bf1781e17f30a594f959671af59a253e9313a9b9</id>
<content type='text'>
Check of the base offset for the IP exists rather than
explicitly checking for how many instances of a particular
IP there are.  This is what soc15.c already does.  Expand
this to nv.c and soc21.c.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: correct cp doorbell range</title>
<updated>2022-05-04T14:43:53Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2022-04-12T20:17:41Z</published>
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<id>urn:sha1:fd0ed91ae8a2b5f3d61a6356b6aaeb2f5b097950</id>
<content type='text'>
1. move MES doorbell inside the mec doorbell range,
   for mes belongs to mec block
2. setting the correct gfx/mec doorbell range, so that
   fw can correctly detect gfx/compute work load to enter/exit
   power saving state.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Tested-and-acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: allocate doorbell index for mes kiq</title>
<updated>2022-05-04T14:43:49Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2021-04-14T08:22:43Z</published>
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<id>urn:sha1:b608e785e1ed7c665b4eeff79e267322eff3c847</id>
<content type='text'>
Allocate a doorbell index for mes kiq queue.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expand cg_flags from u32 to u64</title>
<updated>2022-04-08T21:24:24Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-03-25T10:00:02Z</published>
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<id>urn:sha1:25faeddcf3c3f31f9f43de5c55f7cbdd13d3ebc7</id>
<content type='text'>
With this, we can support more CG flags.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: enable gfx power gating for GC 10.3.7</title>
<updated>2022-03-02T23:40:06Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2022-03-01T06:08:24Z</published>
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<id>urn:sha1:fabe1753851c62d0292a39d89a4a8d7f15c96794</id>
<content type='text'>
Enable gfx power gating for GC 10.3.7.

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblock</title>
<updated>2022-03-02T23:40:06Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2022-03-01T03:22:23Z</published>
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<id>urn:sha1:9a1358bb2ce3738826bce0799d47d6963ccb51bf</id>
<content type='text'>
This will enable the following block clock gating.

 - MC
 - SDMA
 - HDP
 - ATHUB
 - IH
 - VCN/JPEG

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: set mode2 reset for MP1 13.0.8</title>
<updated>2022-02-23T19:26:36Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2022-02-23T06:21:42Z</published>
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<id>urn:sha1:db749b769ff61a42480c377c30df70b8b722041e</id>
<content type='text'>
Set mode2 reset support for MP1 13.0.8.

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: enable gfx10.3.7 clock gating support</title>
<updated>2022-02-23T19:26:36Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2022-02-21T03:14:52Z</published>
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<id>urn:sha1:9e148e8ce29dba471d4812c6a60a3e843f3b6270</id>
<content type='text'>
This will enable the following gfx clock gating.
- Fine clock gating
- Medium Grain clock gating
- 3D Coarse clock gating
- Coarse Grain clock gating
- RLC/CP light sleep clock gating

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add mode2 reset support for smu 13.0.5</title>
<updated>2022-02-23T19:26:36Z</updated>
<author>
<name>Yifan Zhang</name>
<email>yifan1.zhang@amd.com</email>
</author>
<published>2022-02-22T08:22:05Z</published>
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<id>urn:sha1:504390602444a209a52bfdcc59f539e9832079e3</id>
<content type='text'>
This patch adds mode2 reset support for smu 13.0.5.

Signed-off-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
