<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu/nv.c, branch v6.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-05-11T05:04:04Z</updated>
<entry>
<title>drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution</title>
<updated>2023-05-11T05:04:04Z</updated>
<author>
<name>Thong Thai</name>
<email>thong.thai@amd.com</email>
</author>
<published>2023-05-01T15:04:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=476ac50fc30540e29191615a26aaf5f9dee91c49'/>
<id>urn:sha1:476ac50fc30540e29191615a26aaf5f9dee91c49</id>
<content type='text'>
Update the maximum resolution reported for HEVC encoding on VCN 3
devices to reflect its 8K encoding capability.

v2: Also update the max height for H.264 encoding to match spec.
(Ruijing)

Signed-off-by: Thong Thai &lt;thong.thai@amd.com&gt;
Reviewed-by: Ruijing Dong &lt;ruijing.dong@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable doorbell selfring after resize FB BAR</title>
<updated>2023-05-04T02:44:06Z</updated>
<author>
<name>Shane Xiao</name>
<email>shane.xiao@amd.com</email>
</author>
<published>2023-04-25T14:39:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b03f38b9bd90d9eb29951e56f5a4375984c8dffb'/>
<id>urn:sha1:b03f38b9bd90d9eb29951e56f5a4375984c8dffb</id>
<content type='text'>
[Why]
The selfring doorbell aperture will change when resize FB
BAR successfully during gmc sw init, we should reorder
the sequence of enabling doorbell selfring aperture.

[How]
Move enable_doorbell_selfring_aperture from *_common_hw_init
to *_common_late_init.

This fixes the potential issue that GPU ring its own
doorbell when this device is in translated mode when
iommu is on.

v2: Remove *_enable_doorbell_aperture functions (Christian)
v3: Add comments to note that why we need enable doorbell
    selfring late (Christian)

Signed-off-by: Shane Xiao &lt;shane.xiao@amd.com&gt;
Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Tested-by: Xiaomeng Hou &lt;Xiaomeng.Hou@amd.com&gt;
Reviewed-by: Christian K�nig &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge v6.3-rc4 into drm-next</title>
<updated>2023-03-29T14:00:23Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2023-03-29T14:00:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=82bbec189ab34873688484cd14189a5392946fbb'/>
<id>urn:sha1:82bbec189ab34873688484cd14189a5392946fbb</id>
<content type='text'>
I just landed the fence deadline PR from Rob that a bunch of drivers
want/need to apply driver-specific patches. Backmerge -rc4 so that
they don't have to be stuck on -rc2 for no reason at all.

Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: Apply ASPM quirk on Intel ADL + AMD Navi</title>
<updated>2023-03-23T13:34:35Z</updated>
<author>
<name>Kai-Heng Feng</name>
<email>kai.heng.feng@canonical.com</email>
</author>
<published>2023-03-15T12:07:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2b072442f4962231a8516485012bb2d2551ef2fe'/>
<id>urn:sha1:2b072442f4962231a8516485012bb2d2551ef2fe</id>
<content type='text'>
S2idle resume freeze can be observed on Intel ADL + AMD WX5500. This is
caused by commit 0064b0ce85bb ("drm/amd/pm: enable ASPM by default").

The root cause is still not clear for now.

So extend and apply the ASPM quirk from commit e02fe3bc7aba
("drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems"), to
workaround the issue on Navi cards too.

Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default")
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2458
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Retire pcie_gen3_enable function</title>
<updated>2023-03-15T22:45:27Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-03-06T11:34:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4489f0fd9e01efac81d98884d5cf3fa708b9daac'/>
<id>urn:sha1:4489f0fd9e01efac81d98884d5cf3fa708b9daac</id>
<content type='text'>
Not needed since from vi. drop the function so
we don't duplicate code when introduce new asics.

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move to common helper to query soc rev_id</title>
<updated>2023-03-15T22:45:27Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-03-06T07:59:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dabc114e4bac903c365bfe6d7b6e8ed7fa38f8ad'/>
<id>urn:sha1:dabc114e4bac903c365bfe6d7b6e8ed7fa38f8ad</id>
<content type='text'>
Replace soc15, nv, soc21 get_rev_id callback with common
helper so we don't need to duplicate code when introduce
new asics.

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move to common indirect reg access helper</title>
<updated>2023-03-15T22:45:27Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-03-06T07:48:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=65ba96e91b689c23d6fa99c11cfd65965dcddc47'/>
<id>urn:sha1:65ba96e91b689c23d6fa99c11cfd65965dcddc47</id>
<content type='text'>
Replace soc15, nv, soc21 specific callbacks with common
one. so we don't need to duplicate code when introduce
new asics.

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: fix codec array for SR_IOV</title>
<updated>2023-03-14T14:40:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-03-09T03:45:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=45aa07fa832412f1de99194f37fd847915d7e0f6'/>
<id>urn:sha1:45aa07fa832412f1de99194f37fd847915d7e0f6</id>
<content type='text'>
Copy paste error.

Fixes: 384334120b66 ("drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested")
Reported-by: Abaci Robot &lt;abaci@linux.alibaba.com&gt;
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4454
Cc: Jiapeng Chong &lt;jiapeng.chong@linux.alibaba.com&gt;
Acked-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/nv: fix codec array for SR_IOV</title>
<updated>2023-03-13T21:27:49Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-03-09T03:45:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=84b31d484eb9759cb3d8fbbb7a0e191cc097ea28'/>
<id>urn:sha1:84b31d484eb9759cb3d8fbbb7a0e191cc097ea28</id>
<content type='text'>
Copy paste error.

Fixes: 384334120b66 ("drm/amdgpu/nv: don't expose AV1 if VCN0 is harvested")
Reported-by: Abaci Robot &lt;abaci@linux.alibaba.com&gt;
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4454
Cc: Jiapeng Chong &lt;jiapeng.chong@linux.alibaba.com&gt;
Acked-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix error checking in amdgpu_read_mm_registers for nv</title>
<updated>2023-03-10T03:06:19Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-03-07T13:59:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b42fee5e0b44344cfe4c38e61341ee250362c83f'/>
<id>urn:sha1:b42fee5e0b44344cfe4c38e61341ee250362c83f</id>
<content type='text'>
Properly skip non-existent registers as well.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
</feed>
