<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu, branch v4.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2018-09-27T15:01:20Z</updated>
<entry>
<title>drm/amdgpu: Fix vce work queue was not cancelled when suspend</title>
<updated>2018-09-27T15:01:20Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-09-27T12:48:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=61ea6f5831974ebd1a57baffd7cc30600a2e26fc'/>
<id>urn:sha1:61ea6f5831974ebd1a57baffd7cc30600a2e26fc</id>
<content type='text'>
The vce cancel_delayed_work_sync never be called.
driver call the function in error path.

This caused the A+A suspend hang when runtime pm enebled.
As we will visit the smu in the idle queue. this will cause
smu hang because the dgpu has been suspend, and the dgpu also
will be waked up. As the smu has been hang, so the dgpu resume
will failed.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9</title>
<updated>2018-09-20T15:25:17Z</updated>
<author>
<name>Yong Zhao</name>
<email>yong.zhao@amd.com</email>
</author>
<published>2018-09-13T01:42:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=15426dbb65c5b37680d27e84d58a1ed3b8532518'/>
<id>urn:sha1:15426dbb65c5b37680d27e84d58a1ed3b8532518</id>
<content type='text'>
CWSR fails on Raven if the control stack is MTYPE_UC, which is used
for regular GART mappings. As a workaround we map it using MTYPE_NC.

The MEC firmware expects the control stack at one page offset from the
start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU
added a memory allocation flag just for this purpose.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix SDMA HQD destroy error on gfx_v7</title>
<updated>2018-09-20T15:25:01Z</updated>
<author>
<name>Amber Lin</name>
<email>Amber.Lin@amd.com</email>
</author>
<published>2018-09-13T01:42:18Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=caaa4c8a6be2a275bd14f2369ee364978ff74704'/>
<id>urn:sha1:caaa4c8a6be2a275bd14f2369ee364978ff74704</id>
<content type='text'>
A wrong register bit was examinated for checking SDMA status so it reports
false failures. This typo only appears on gfx_v7. gfx_v8 checks the correct
bit.

Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Amber Lin &lt;Amber.Lin@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new polaris pci id</title>
<updated>2018-09-20T03:35:23Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2018-09-18T20:28:24Z</published>
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<id>urn:sha1:30f3984ede683b98a4e8096e200df78bf0609b4f</id>
<content type='text'>
Add new pci id.

Reviewed-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: fix error handling in amdgpu_cs_user_fence_chunk</title>
<updated>2018-09-11T21:35:00Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-09-10T13:52:55Z</published>
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<id>urn:sha1:0165de983272d1fae0809ed9db47c46a412279bc</id>
<content type='text'>
Slowly leaking memory one page at a time :)

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move PSP init prior to IH in gpu reset</title>
<updated>2018-09-11T03:58:21Z</updated>
<author>
<name>Emily Deng</name>
<email>Emily.Deng@amd.com</email>
</author>
<published>2018-09-10T09:51:31Z</published>
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<id>urn:sha1:3a74987b24279d242d17f522f8435f1942a3c948</id>
<content type='text'>
since we use PSP to program IH regs now

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix SDMA hang in prt mode v2</title>
<updated>2018-09-11T03:56:27Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2018-09-07T05:50:31Z</published>
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<id>urn:sha1:68ebc13ea40656fddd3803735d621921a2d74a5e</id>
<content type='text'>
Fix SDMA hang in prt mode, clear XNACK_WATERMARK in reg SDMA0_UTCL1_WATERMK to avoid the issue

Affected ASICs: VEGA10 VEGA12 RV1 RV2

v2: add reg clear for SDMA1

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Tested-by: Yukun Li &lt;yukun1.li@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix amdgpu_mn_unlock() in the CS error path</title>
<updated>2018-09-11T03:53:29Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2018-09-03T08:51:51Z</published>
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<id>urn:sha1:b463d4e53ca9bdbf227e19b477fbfcdedaa14c84</id>
<content type='text'>
Avoid unlocking a lock we never locked.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-fixes-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-fixes</title>
<updated>2018-08-30T01:34:14Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2018-08-30T01:30:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=185c3cfacafded57663dedd50bdab53fff0d8bc3'/>
<id>urn:sha1:185c3cfacafded57663dedd50bdab53fff0d8bc3</id>
<content type='text'>
Fixes for 4.19:
- SR-IOV fixes
- Kasan and page fault fix on device removal
- S3 stability fix for CZ/ST
- VCE regression fixes for CIK parts
- Avoid holding the mn_lock when allocating memory
- DC memory leak fix
- BO eviction fix

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Alex Deucher &lt;alexdeucher@gmail.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20180829202555.2653-1-alexander.deucher@amd.com
</content>
</entry>
<entry>
<title>drm/amdgpu: Need to set moved to true when evict bo</title>
<updated>2018-08-28T17:42:48Z</updated>
<author>
<name>Emily Deng</name>
<email>Emily.Deng@amd.com</email>
</author>
<published>2018-08-28T12:52:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6ddd9769db4fc11a98bd7e58be1764e47fdb8384'/>
<id>urn:sha1:6ddd9769db4fc11a98bd7e58be1764e47fdb8384</id>
<content type='text'>
Fix the VMC page fault when the running sequence is as below:
1.amdgpu_gem_create_ioctl
2.ttm_bo_swapout-&gt;amdgpu_vm_bo_invalidate, as not called
amdgpu_vm_bo_base_init, so won't called
list_add_tail(&amp;base-&gt;bo_list, &amp;bo-&gt;va). Even the bo was evicted,
it won't set the bo_base-&gt;moved.
3.drm_gem_open_ioctl-&gt;amdgpu_vm_bo_base_init, here only called
list_move_tail(&amp;base-&gt;vm_status, &amp;vm-&gt;evicted), but not set the
bo_base-&gt;moved.
4.amdgpu_vm_bo_map-&gt;amdgpu_vm_bo_insert_map, as the bo_base-&gt;moved is
not set true, the function amdgpu_vm_bo_insert_map will call
list_move(&amp;bo_va-&gt;base.vm_status, &amp;vm-&gt;moved)
5.amdgpu_cs_ioctl won't validate the swapout bo, as it is only in the
moved list, not in the evict list. So VMC page fault occurs.

Signed-off-by: Emily Deng &lt;Emily.Deng@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
