<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu, branch v4.2</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.2</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.2'/>
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<updated>2015-08-12T16:24:04Z</updated>
<entry>
<title>Revert "drm/amdgpu: Configure doorbell to maximum slots"</title>
<updated>2015-08-12T16:24:04Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-08-10T15:08:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b8826b0cbf47ecfc9fdefdbf8c7bbb308e117005'/>
<id>urn:sha1:b8826b0cbf47ecfc9fdefdbf8c7bbb308e117005</id>
<content type='text'>
This reverts commit 78ad5cdd21f0d614983fc397338944e797ec70b9.
This commit breaks dpm and suspend/resume on CZ.
</content>
</entry>
<entry>
<title>drm/amdgpu: add context buffer size check for HEVC</title>
<updated>2015-08-12T16:24:03Z</updated>
<author>
<name>Boyuan Zhang</name>
<email>boyuan.zhang@amd.com</email>
</author>
<published>2015-08-05T18:03:48Z</published>
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<id>urn:sha1:8c8bac59dda0c41c7dd289d443ac42b7b72d31b0</id>
<content type='text'>
Signed-off-by: Boyuan Zhang &lt;boyuan.zhang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: set fw_version and feature_version for smu fw loading</title>
<updated>2015-08-05T18:26:50Z</updated>
<author>
<name>Jammy Zhou</name>
<email>Jammy.Zhou@amd.com</email>
</author>
<published>2015-08-04T03:44:19Z</published>
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<id>urn:sha1:595fd013f795daeed0c7ddda02d8e0c51d8ce76c</id>
<content type='text'>
The fw_version and feature_verion should be set correctly when the
firmwares are loaded by SMU on Tonga/Carrzio/Iceland

Signed-off-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add feature version for SDMA ucode</title>
<updated>2015-08-05T18:26:50Z</updated>
<author>
<name>Jammy Zhou</name>
<email>Jammy.Zhou@amd.com</email>
</author>
<published>2015-08-04T02:50:47Z</published>
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<id>urn:sha1:cfa2104fbcb87ab0abbdaba608087df1e24fe195</id>
<content type='text'>
Signed-off-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add feature version for RLC and MEC v2</title>
<updated>2015-08-05T18:26:49Z</updated>
<author>
<name>Jammy Zhou</name>
<email>Jammy.Zhou@amd.com</email>
</author>
<published>2015-08-04T02:43:50Z</published>
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<id>urn:sha1:351643d7dd8a48b1053aac5fe3a1aebac614c301</id>
<content type='text'>
Expose feature version to user space for RLC/MEC/MEC2 ucode as well

v2: fix coding style

Signed-off-by: Jammy Zhou &lt;Jammy.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increment queue when iterating on this variable.</title>
<updated>2015-08-05T18:26:48Z</updated>
<author>
<name>Nicolas Iooss</name>
<email>nicolas.iooss_linux@m4x.org</email>
</author>
<published>2015-08-01T13:55:38Z</published>
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<id>urn:sha1:0fd64291031d3587753b8adc53123b277855c777</id>
<content type='text'>
gfx_v7_0_print_status contains a for loop on variable queue which does
not update this variable between each iteration.  This is bug is
reported by clang while building allmodconfig LLVMLinux on x86_64:

    drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:5126:19: error: variable
    'queue' used in loop condition not modified in loop body
    [-Werror,-Wloop-analysis]
                for (queue = 0; queue &lt; 8; i++) {
                                ^~~~~

Fix this by incrementing variable queue instead of i in this loop.

Signed-off-by: Nicolas Iooss &lt;nicolas.iooss_linux@m4x.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix rb setting for CZ</title>
<updated>2015-08-05T18:26:48Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2015-07-09T02:23:38Z</published>
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<id>urn:sha1:a0e2f50bdb588d91a553f2f6bd56be7bedc94b1a</id>
<content type='text'>
Always set num_rbs to 2 for CZ.  The 1 RB parts are often harvest
configs.  The will get sorted out in mesa when we program
PA_SC_RASTER_CONFIG[_1].

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new parameter to seperate map and unmap</title>
<updated>2015-07-29T20:06:45Z</updated>
<author>
<name>monk.liu</name>
<email>monk.liu@amd.com</email>
</author>
<published>2015-07-22T05:29:28Z</published>
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<id>urn:sha1:194a33643b1161fe7a054fa9bf43875ae0f6e1e8</id>
<content type='text'>
Signed-off-by: monk.liu &lt;monk.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: hdp_flush is not needed for inside IB</title>
<updated>2015-07-29T20:06:17Z</updated>
<author>
<name>monk.liu</name>
<email>monk.liu@amd.com</email>
</author>
<published>2015-07-17T09:10:09Z</published>
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<id>urn:sha1:e722b71a540362eebdbae060430dc5b06b990c38</id>
<content type='text'>
hdp flush is not needed for IBs that dispatched from kernel inside
because there is no video memory host access

Signed-off-by: monk.liu &lt;monk.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: different emit_ib for gfx and compute</title>
<updated>2015-07-29T20:05:57Z</updated>
<author>
<name>monk.liu</name>
<email>monk.liu@amd.com</email>
</author>
<published>2015-07-15T09:21:45Z</published>
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<id>urn:sha1:93323131d66db68802e646204c0562cddc81a651</id>
<content type='text'>
compute ring didn't use const engine byfar, so ignore CE things in
compute routine

Signed-off-by: monk.liu &lt;monk.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
</content>
</entry>
</feed>
