linux/drivers/gpu/drm/amd/amdgpu, branch v5.12Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v5.122021-04-21T15:19:26Zdrm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish2021-04-21T15:19:26ZJiansong ChenJiansong.Chen@amd.com2021-04-19T08:33:22Zurn:sha1:24d034528ef06ad94cfcf4394beac0443ab1b16d
dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: reserve fence slot to update page table2021-04-21T15:10:35ZPhilip YangPhilip.Yang@amd.com2021-04-01T04:22:23Zurn:sha1:d42a5b639d15622ece5b9dd12dafd9776efa2593
Forgot to reserve a fence slot to use sdma to update page table, cause
below kernel BUG backtrace to handle vm retry fault while application is
exiting.
[ 133.048143] kernel BUG at /home/yangp/git/compute_staging/kernel/drivers/dma-buf/dma-resv.c:281!
[ 133.048487] Workqueue: events amdgpu_irq_handle_ih1 [amdgpu]
[ 133.048506] RIP: 0010:dma_resv_add_shared_fence+0x204/0x280
[ 133.048672] amdgpu_vm_sdma_commit+0x134/0x220 [amdgpu]
[ 133.048788] amdgpu_vm_bo_update_range+0x220/0x250 [amdgpu]
[ 133.048905] amdgpu_vm_handle_fault+0x202/0x370 [amdgpu]
[ 133.049031] gmc_v9_0_process_interrupt+0x1ab/0x310 [amdgpu]
[ 133.049165] ? kgd2kfd_interrupt+0x9a/0x180 [amdgpu]
[ 133.049289] ? amdgpu_irq_dispatch+0xb6/0x240 [amdgpu]
[ 133.049408] amdgpu_irq_dispatch+0xb6/0x240 [amdgpu]
[ 133.049534] amdgpu_ih_process+0x9b/0x1c0 [amdgpu]
[ 133.049657] amdgpu_irq_handle_ih1+0x21/0x60 [amdgpu]
[ 133.049669] process_one_work+0x29f/0x640
[ 133.049678] worker_thread+0x39/0x3f0
[ 133.049685] ? process_one_work+0x640/0x640
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.11.x
drm/amdgpu: Fix size overflow2021-04-08T04:36:40Zxinhui panxinhui.pan@amd.com2021-04-07T11:29:39Zurn:sha1:1b0b6e939f112949089e32ec89fd27796677263a
ttm->num_pages is uint32. Hit overflow when << PAGE_SHIFT directly
Fixes: 230c079fdcf4 ("drm/ttm: make num_pages uint32_t")
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: check alignment on CPU page for bo map2021-04-01T01:53:38ZXℹ Ruoyaoxry111@mengyan1223.wang2021-03-30T15:33:34Zurn:sha1:e3512fb67093fabdf27af303066627b921ee9bd8
The page table of AMDGPU requires an alignment to CPU page so we should
check ioctl parameters for it. Return -EINVAL if some parameter is
unaligned to CPU page, instead of corrupt the page table sliently.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Xi Ruoyao <xry111@mengyan1223.wang>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: Set a suitable dev_info.gart_page_size2021-04-01T01:53:38ZHuacai Chenchenhc@lemote.com2021-03-30T15:33:33Zurn:sha1:566c6e25f957ebdb0b6e8073ee291049118f47fb
In Mesa, dev_info.gart_page_size is used for alignment and it was
set to AMDGPU_GPU_PAGE_SIZE(4KB). However, the page table of AMDGPU
driver requires an alignment on CPU pages. So, for non-4KB page system,
gart_page_size should be max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE).
Signed-off-by: Rui Wang <wangr@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Link: https://github.com/loongson-community/linux-stable/commit/caa9c0a1
[Xi: rebased for drm-next, use max_t for checkpatch,
and reworded commit message.]
Signed-off-by: Xi Ruoyao <xry111@mengyan1223.wang>
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1549
Tested-by: Dan Horák <dan@danny.cz>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: fix offset calculation in amdgpu_vm_bo_clear_mappings()2021-03-29T18:05:49ZNirmoy Dasnirmoy.das@amd.com2021-03-26T15:08:10Zurn:sha1:5e61b84f9d3ddfba73091f9fbc940caae1c9eb22
Offset calculation wasn't correct as start addresses are in pfn
not in bytes.
CC: stable@vger.kernel.org
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add additional Sienna Cichlid PCI ID2021-03-24T04:29:37ZAlex Deucheralexander.deucher@amd.com2021-03-18T20:44:10Zurn:sha1:c933b111094f2818571fc51b81b98ee0d370c035
Add new DID.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: skip kfd suspend/resume for S0ix2021-03-22T19:28:20ZAlex Deucheralexander.deucher@amd.com2021-03-17T02:02:14Zurn:sha1:ac5789ef927006a8449ea235a866922b2d8f8290
GFX is in gfxoff mode during s0ix so we shouldn't need to
actually tear anything down and restore it.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: drop S0ix checks around CG/PG in suspend2021-03-22T19:28:10ZAlex Deucheralexander.deucher@amd.com2021-03-16T18:18:30Zurn:sha1:264705005e6bc7f484652c1d7aee798034c82e12
We handle it properly within the CG/PG functions directly
now.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: skip CG/PG for gfx during S0ix2021-03-22T19:27:59ZPratik VishwakarmaPratik.Vishwakarma@amd.com2021-03-16T18:15:44Zurn:sha1:10cb67eb8a1b21419a7cd8e12f002a36bfef12fd
Not needed as the device is in gfxoff state so the CG/PG state
is handled just like it would be for gfxoff during runtime gfxoff.
This should also prevent delays on resume.
Reworked from Pratik's original patch (Alex)
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>