<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu, branch v5.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-08-27T17:25:20Z</updated>
<entry>
<title>drm/amdgpu: fix GFXOFF on Picasso and Raven2</title>
<updated>2019-08-27T17:25:20Z</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2019-08-27T14:59:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=41940ff50f6c347f3541163702566cd526200d98'/>
<id>urn:sha1:41940ff50f6c347f3541163702566cd526200d98</id>
<content type='text'>
For picasso(adev-&gt;pdev-&gt;device == 0x15d8)&amp;raven2(adev-&gt;rev_id &gt;= 0x8),
firmware is sufficient to support gfxoff.
In commit 98f58ada2d37e, for picasso&amp;raven2,
return directly and cause gfxoff disabled.

Fixes: 98f58ada2d37 ("drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible")
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Add APTX quirk for Dell Latitude 5495</title>
<updated>2019-08-27T17:24:40Z</updated>
<author>
<name>Kai-Heng Feng</name>
<email>kai.heng.feng@canonical.com</email>
</author>
<published>2019-08-27T09:33:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=317a3aaef94d73ba6be88aea11b41bb631b2d581'/>
<id>urn:sha1:317a3aaef94d73ba6be88aea11b41bb631b2d581</id>
<content type='text'>
Needs ATPX rather than _PR3 to really turn off the dGPU. This can save
~5W when dGPU is runtime-suspended.

Signed-off-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: fix dma_fence_wait without reference</title>
<updated>2019-08-26T20:33:36Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-08-16T12:56:35Z</published>
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<id>urn:sha1:42068e1ef961c719f967dbbb4ddcb394a0ba7917</id>
<content type='text'>
We need to grab a reference to the fence we wait for.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Chunming Zhou &lt;david1.zhou@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctl</title>
<updated>2019-08-21T22:32:39Z</updated>
<author>
<name>Nicolai Hähnle</name>
<email>nicolai.haehnle@amd.com</email>
</author>
<published>2019-08-20T13:39:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1a701ea924815b0518733aa8d5d05c1f6fa87062'/>
<id>urn:sha1:1a701ea924815b0518733aa8d5d05c1f6fa87062</id>
<content type='text'>
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or
TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the
allocated array as well as the reference counts of sync objects are leaked.

Signed-off-by: Nicolai Hähnle &lt;nicolai.haehnle@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: disable MMHUB PG for navi10</title>
<updated>2019-08-21T22:32:24Z</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2019-08-20T07:11:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=221a2bdbd5d3871a5f41d912b2f06cc02e8f8b38'/>
<id>urn:sha1:221a2bdbd5d3871a5f41d912b2f06cc02e8f8b38</id>
<content type='text'>
Disable MMHUB PG for navi10 according to the production requirement.

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possible</title>
<updated>2019-08-21T22:29:49Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-08-15T13:27:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=98f58ada2d37e68125c056f1fc005748251879c2'/>
<id>urn:sha1:98f58ada2d37e68125c056f1fc005748251879c2</id>
<content type='text'>
We need to set certain power gating flags after we determine
if the firmware version is sufficient to support gfxoff.
Previously we set the pg flags in early init, but we later
we might have disabled gfxoff if the firmware versions didn't
support it.  Move adding the additional pg flags after we
determine whether or not to support gfxoff.

Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)")
Tested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Tested-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: fix gfx9 soft recovery</title>
<updated>2019-08-13T03:01:17Z</updated>
<author>
<name>Pierre-Eric Pelloux-Prayer</name>
<email>pierre-eric.pelloux-prayer@amd.com</email>
</author>
<published>2019-08-06T16:27:26Z</published>
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<id>urn:sha1:17b6d2d528542bc60ad400add35728b2259b3cc1</id>
<content type='text'>
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail.

v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET

Signed-off-by: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>Revert "drm/amdgpu: fix transform feedback GDS hang on gfx10 (v2)"</title>
<updated>2019-08-07T04:28:41Z</updated>
<author>
<name>Marek Olšák</name>
<email>marek.olsak@amd.com</email>
</author>
<published>2019-08-02T21:44:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d9dfe768b3f30faa8340cbf34196668714780c3c'/>
<id>urn:sha1:d9dfe768b3f30faa8340cbf34196668714780c3c</id>
<content type='text'>
This reverts commit 9ed2c993d723129f85101e51b2ccc36ef5400a67.

SET_CONFIG_REG writes to memory if register shadowing is enabled,
causing a VM fault.

NGG streamout is unstable anyway, so all UMDs should use legacy
streamout. I think Mesa is the only driver using NGG streamout.

Signed-off-by: Marek Olšák &lt;marek.olsak@amd.com&gt;
Reviewed-by: Le Ma &lt;Le.Ma@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: pin the csb buffer on hw init for gfx v8</title>
<updated>2019-08-06T20:04:40Z</updated>
<author>
<name>Likun Gao</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2019-08-02T07:18:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=72cda9bb5e219aea0f2f62f56ae05198c59022a7'/>
<id>urn:sha1:72cda9bb5e219aea0f2f62f56ae05198c59022a7</id>
<content type='text'>
Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Tested-by: Paul Gover &lt;pmw.gover@yahoo.co.uk&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0</title>
<updated>2019-08-02T15:36:35Z</updated>
<author>
<name>Thong Thai</name>
<email>thong.thai@amd.com</email>
</author>
<published>2019-07-25T15:26:56Z</published>
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<id>urn:sha1:d1836f3813ee0742a2067d5f4d78e811d2b76d9d</id>
<content type='text'>
VCN 2.0 firmware now requires a packet start command to be sent before
any other decode ring buffer command.

Signed-off-by: Thong Thai &lt;thong.thai@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
