<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu, branch v5.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-03-27T02:33:23Z</updated>
<entry>
<title>Merge tag 'drm-misc-fixes-2020-03-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes</title>
<updated>2020-03-27T02:33:23Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2020-03-27T02:33:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5117c363eb213d5503f5b7e39c9bfafd46388184'/>
<id>urn:sha1:5117c363eb213d5503f5b7e39c9bfafd46388184</id>
<content type='text'>
drm-misc-fixes for v5.6:
- SG fixes for prime, radeon and amdgpu.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Maarten Lankhorst &lt;maarten.lankhorst@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/ef10e822-76dd-125d-ec1f-9a78c5f76bc3@linux.intel.com
</content>
</entry>
<entry>
<title>drm/amdgpu: fix scatter-gather mapping with user pages</title>
<updated>2020-03-25T16:10:40Z</updated>
<author>
<name>Shane Francis</name>
<email>bigbeeshane@gmail.com</email>
</author>
<published>2020-03-25T09:07:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0199172f933342d8b1011aae2054a695c25726f4'/>
<id>urn:sha1:0199172f933342d8b1011aae2054a695c25726f4</id>
<content type='text'>
Calls to dma_map_sg may return less segments / entries than requested
if they fall on page bounderies. The old implementation did not
support this use case.

Fixes: be62dbf554c5 ("iommu/amd: Convert AMD iommu driver to the dma-iommu api")
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206461
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=206895
Bug: https://gitlab.freedesktop.org/drm/amd/issues/1056
Signed-off-by: Shane Francis &lt;bigbeeshane@gmail.com&gt;
Reviewed-by: Michael J. Ruhl &lt;michael.j.ruhl@intel.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20200325090741.21957-3-bigbeeshane@gmail.com
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: fix typo for vcn2.5/jpeg2.5 idle check</title>
<updated>2020-03-18T22:21:57Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2020-03-18T21:12:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a3c33e7a4a116f8715c0ef0e668e6aeff009c762'/>
<id>urn:sha1:a3c33e7a4a116f8715c0ef0e668e6aeff009c762</id>
<content type='text'>
fix typo for vcn2.5/jpeg2.5 idle check

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix typo for vcn2/jpeg2 idle check</title>
<updated>2020-03-18T22:21:45Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2020-03-18T21:10:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b5689d22aa6d815f29d34f8cbd708f9d34eed70a'/>
<id>urn:sha1:b5689d22aa6d815f29d34f8cbd708f9d34eed70a</id>
<content type='text'>
fix typo for vcn2/jpeg2 idle check

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix typo for vcn1 idle check</title>
<updated>2020-03-18T22:21:18Z</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2020-03-18T21:09:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=acfc62dc68770aa665cc606891f6df7d6d1e52c0'/>
<id>urn:sha1:acfc62dc68770aa665cc606891f6df7d6d1e52c0</id>
<content type='text'>
fix typo for vcn1 idle check

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add fbdev suspend/resume on gpu reset</title>
<updated>2020-03-13T13:20:31Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-03-11T06:15:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=063e768ebd27d3ec0d6908b7f8ea9b0a732b9949'/>
<id>urn:sha1:063e768ebd27d3ec0d6908b7f8ea9b0a732b9949</id>
<content type='text'>
This can fix the baco reset failure seen on Navi10.
And this should be a low risk fix as the same sequence
is already used for system suspend/resume.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Fix GPR read from debugfs (v2)</title>
<updated>2020-03-13T13:20:31Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2020-03-10T12:40:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5bbc6604a62814511c32f2e39bc9ffb2c1b92cbe'/>
<id>urn:sha1:5bbc6604a62814511c32f2e39bc9ffb2c1b92cbe</id>
<content type='text'>
The offset into the array was specified in bytes but should
be in terms of 32-bit words.  Also prevent large reads that
would also cause a buffer overread.

v2:  Read from correct offset from internal storage buffer.

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: correct ROM_INDEX/DATA offset for VEGA20</title>
<updated>2020-03-09T20:42:28Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2020-03-04T09:03:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f1c2cd3f8fb959123a9beba18c0e8112dcb2e137'/>
<id>urn:sha1:f1c2cd3f8fb959123a9beba18c0e8112dcb2e137</id>
<content type='text'>
The ROMC_INDEX/DATA offset was changed to e4/e5 since
from smuio_v11 (vega20/arcturus).

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Tested-by: Candice Li &lt;Candice.Li@amd.com&gt;
Reviewed-by: Candice Li &lt;Candice.Li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: disable 3D pipe 1 on Navi1x</title>
<updated>2020-03-05T14:41:55Z</updated>
<author>
<name>Tianci.Yin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2020-02-28T09:10:21Z</published>
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<id>urn:sha1:194bcf35bce4a236059816bc41b3db9c9c92a1bb</id>
<content type='text'>
[why]
CP firmware decide to skip setting the state for 3D pipe 1 for Navi1x as there
is no use case.

[how]
Disable 3D pipe 1 on Navi1x.

Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Tianci.Yin &lt;tianci.yin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: clean wptr on wb when gpu recovery</title>
<updated>2020-03-05T05:50:07Z</updated>
<author>
<name>Yintian Tao</name>
<email>yttao@amd.com</email>
</author>
<published>2020-02-28T06:24:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2ab7e274b86739f4ceed5d94b6879f2d07b2802f'/>
<id>urn:sha1:2ab7e274b86739f4ceed5d94b6879f2d07b2802f</id>
<content type='text'>
The TDR will be randomly failed due to compute ring
test failure. If the compute ring wptr &amp; 0x7ff(ring_buf_mask)
is 0x100 then after map mqd the compute ring rptr will be
synced with 0x100. And the ring test packet size is also 0x100.
Then after invocation of amdgpu_ring_commit, the cp will not
really handle the packet on the ring buffer because rptr is equal to wptr.

Signed-off-by: Yintian Tao &lt;yttao@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
