<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-09-18T18:59:41Z</updated>
<entry>
<title>drm/amdgpu: suspend KFD and KGD user queues for S0ix</title>
<updated>2025-09-18T18:59:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-09-17T16:42:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9272bb34b066993f5f468b219b4a26ba3f2b25a1'/>
<id>urn:sha1:9272bb34b066993f5f468b219b4a26ba3f2b25a1</id>
<content type='text'>
We need to make sure the user queues are preempted so
GFX can enter gfxoff.

Reviewed-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Tested-by: David Perry &lt;david.perry@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit f8b367e6fa1716cab7cc232b9e3dff29187fc99d)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdkfd: add proper handling for S0ix</title>
<updated>2025-09-18T18:59:24Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-09-17T16:42:09Z</published>
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<id>urn:sha1:2ade36eaa9ac05e4913e9785df19c2cde8f912fb</id>
<content type='text'>
When in S0i3, the GFX state is retained, so all we need to do
is stop the runlist so GFX can enter gfxoff.

Reviewed-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Tested-by: David Perry &lt;david.perry@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 4bfa8609934dbf39bbe6e75b4f971469384b50b1)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx11: Add Cleaner Shader Support for GFX11.0.1/11.0.4 GPUs</title>
<updated>2025-09-15T21:23:42Z</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2025-09-10T06:57:05Z</published>
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<id>urn:sha1:c1b6b8c7706354b73196649c46b5e6d4d61c2f5c</id>
<content type='text'>
Enable the cleaner shader for additional GFX11.0.1/11.0.4 series GPUs to
ensure data isolation among GPU tasks. The cleaner shader is tasked with
clearing the Local Data Store (LDS), Vector General Purpose Registers
(VGPRs), and Scalar General Purpose Registers (SGPRs), which helps avoid
data leakage and guarantees the accuracy of computational results.

This update extends cleaner shader support to GFX11.0.1/11.0.4 GPUs,
previously available for GFX11.0.3. It enhances security by clearing GPU
memory between processes and maintains a consistent GPU state across KGD
and KFD workloads.

Cc: Wasee Alam &lt;wasee.alam@amd.com&gt;
Cc: Mario Sopena-Novales &lt;mario.novales@amd.com&gt;
Cc: Christian König &lt;christian.koenig@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 0a71ceb27f88a944c2de2808b67b2f46ac75076b)
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time</title>
<updated>2025-09-09T20:42:26Z</updated>
<author>
<name>David Rosca</name>
<email>david.rosca@amd.com</email>
</author>
<published>2025-08-18T07:18:37Z</published>
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<id>urn:sha1:3318f2d20ce48849855df5e190813826d0bc3653</id>
<content type='text'>
There is no reason to require this to happen on first submitted IB only.
We need to wait for the queue to be idle, but it can be done at any
time (including when there are multiple video sessions active).

Signed-off-by: David Rosca &lt;david.rosca@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 8908fdce0634a623404e9923ed2f536101a39db5)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn4: Fix IB parsing with multiple engine info packages</title>
<updated>2025-09-09T20:41:49Z</updated>
<author>
<name>David Rosca</name>
<email>david.rosca@amd.com</email>
</author>
<published>2025-08-18T07:06:58Z</published>
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<id>urn:sha1:2b10cb58d7a3fd621ec9b2ba765a092e562ef998</id>
<content type='text'>
There can be multiple engine info packages in one IB and the first one
may be common engine, not decode/encode.
We need to parse the entire IB instead of stopping after finding first
engine info.

Signed-off-by: David Rosca &lt;david.rosca@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit dc8f9f0f45166a6b37864e7a031c726981d6e5fc)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Declare isp firmware binary file</title>
<updated>2025-09-09T20:41:15Z</updated>
<author>
<name>Pratap Nirujogi</name>
<email>pratap.nirujogi@amd.com</email>
</author>
<published>2025-09-03T20:00:24Z</published>
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<id>urn:sha1:857ccfc19f9be1269716f3d681650c1bd149a656</id>
<content type='text'>
Declare isp firmware file isp_4_1_1.bin required by isp4.1.1 device.

Suggested-by: Alexey Zagorodnikov &lt;xglooom@gmail.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Pratap Nirujogi &lt;pratap.nirujogi@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit d97b74a833eba1f4f69f67198fd98ef036c0e5f9)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: fix a memory leak in fence cleanup when unloading</title>
<updated>2025-09-09T20:38:26Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-09-04T16:35:05Z</published>
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<id>urn:sha1:7838fb5f119191403560eca2e23613380c0e425e</id>
<content type='text'>
Commit b61badd20b44 ("drm/amdgpu: fix usage slab after free")
reordered when amdgpu_fence_driver_sw_fini() was called after
that patch, amdgpu_fence_driver_sw_fini() effectively became
a no-op as the sched entities we never freed because the
ring pointers were already set to NULL.  Remove the NULL
setting.

Reported-by: Lin.Cao &lt;lincao12@amd.com&gt;
Cc: Vitaly Prosyak &lt;vitaly.prosyak@amd.com&gt;
Cc: Christian König &lt;christian.koenig@amd.com&gt;
Fixes: b61badd20b44 ("drm/amdgpu: fix usage slab after free")
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit a525fa37aac36c4591cc8b07ae8957862415fbd5)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>amd/amdkfd: correct mem limit calculation for small APUs</title>
<updated>2025-09-09T16:28:28Z</updated>
<author>
<name>Yifan Zhang</name>
<email>yifan1.zhang@amd.com</email>
</author>
<published>2025-08-20T08:10:51Z</published>
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<id>urn:sha1:53503556273a5ead8b75534085e2dcb46e96f883</id>
<content type='text'>
Current mem limit check leaks some GTT memory (reserved_for_pt
reserved_for_ras + adev-&gt;vram_pin_size) for small APUs.

Since carveout VRAM is tunable on APUs, there are three case
regarding the carveout VRAM size relative to GTT:

1. 0 &lt; carveout &lt; gtt
   apu_prefer_gtt = true, is_app_apu = false

2. carveout &gt; gtt / 2
   apu_prefer_gtt = false, is_app_apu = false

3. 0 = carveout
   apu_prefer_gtt = true, is_app_apu = true

It doesn't make sense to check below limitation in case 1
(default case, small carveout) because the values in the below
expression are mixed with carveout and gtt.

adev-&gt;kfd.vram_used[xcp_id] + vram_needed &gt;
    vram_size - reserved_for_pt - reserved_for_ras -
    atomic64_read(&amp;adev-&gt;vram_pin_size)

gtt: kfd.vram_used, vram_needed, vram_size
carveout: reserved_for_pt, reserved_for_ras, adev-&gt;vram_pin_size

In case 1, vram allocation will go to gtt domain, skip vram check
since ttm_mem_limit check already cover this allocation.

Signed-off-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit fa7c99f04f6dd299388e9282812b14e95558ac8e)
</content>
</entry>
<entry>
<title>drm/amdgpu: Wait for bootloader after PSPv11 reset</title>
<updated>2025-09-08T15:05:53Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-07-18T13:20:58Z</published>
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<id>urn:sha1:440cec4ca1c242d72e309a801995584a55af25c6</id>
<content type='text'>
Some PSPv11 SOCs take a longer time for PSP based mode-1 reset. Instead
of checking for C2PMSG_33 status, add the callback wait_for_bootloader.
Wait for bootloader to be back to steady state is already part of the
generic mode-1 reset flow. Increase the retry count for bootloader wait
and also fix the mask to prevent fake pass.

Fixes: 8345a71fc54b ("drm/amdgpu: Add more checks to PSP mailbox")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4531
Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 32f73741d6ee41fd5db8791c1163931e313d0fdc)
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Fix missing error return on kzalloc failure</title>
<updated>2025-09-03T20:27:56Z</updated>
<author>
<name>Colin Ian King</name>
<email>colin.i.king@gmail.com</email>
</author>
<published>2025-09-02T12:40:50Z</published>
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<id>urn:sha1:467e00b30dfe75c4cfc2197ceef1fddca06adc25</id>
<content type='text'>
Currently the kzalloc failure check just sets reports the failure
and sets the variable ret to -ENOMEM, which is not checked later
for this specific error. Fix this by just returning -ENOMEM rather
than setting ret.

Fixes: 4fb930715468 ("drm/amd/amdgpu: remove redundant host to psp cmd buf allocations")
Signed-off-by: Colin Ian King &lt;colin.i.king@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 1ee9d1a0962c13ba5ab7e47d33a80e3b8dc4b52e)
</content>
</entry>
</feed>
