<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdgpu, branch v6.18</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.18</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.18'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-11-26T17:34:16Z</updated>
<entry>
<title>drm/amdgpu: fix cyan_skillfish2 gpu info fw handling</title>
<updated>2025-11-26T17:34:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-11-26T14:40:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7fa666ab07ba9e08f52f357cb8e1aad753e83ac6'/>
<id>urn:sha1:7fa666ab07ba9e08f52f357cb8e1aad753e83ac6</id>
<content type='text'>
If the board supports IP discovery, we don't need to
parse the gpu info firmware.

Backport to 6.18.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4721
Fixes: fa819e3a7c1e ("drm/amdgpu: add support for cyan skillfish gpu_info")
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 5427e32fa3a0ba9a016db83877851ed277b065fb)
</content>
</entry>
<entry>
<title>drm/amdgpu: attach tlb fence to the PTs update</title>
<updated>2025-11-26T17:33:05Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2025-10-31T09:02:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b4a7f4e7ad2b120a94f3111f92a11520052c762d'/>
<id>urn:sha1:b4a7f4e7ad2b120a94f3111f92a11520052c762d</id>
<content type='text'>
Ensure the userq TLB flush is emitted only after
the VM update finishes and the PT BOs have been
annotated with bookkeeping fences.

Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit f3854e04b708d73276c4488231a8bd66d30b4671)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: reserve vm invalidation engine for uni_mes</title>
<updated>2025-11-24T18:25:31Z</updated>
<author>
<name>Michael Chen</name>
<email>michael.chen@amd.com</email>
</author>
<published>2025-11-13T17:56:43Z</published>
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<id>urn:sha1:971fb57429df5aa4e6efc796f7841e0d10b1e83c</id>
<content type='text'>
Reserve vm invalidation engine 6 when uni_mes enabled. It
is used in processing tlb flush request from host.

Signed-off-by: Michael Chen &lt;michael.chen@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Shaoyun liu &lt;Shaoyun.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 873373739b9b150720ea2c5390b4e904a4d21505)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Add sriov vf check for VCN per queue reset support.</title>
<updated>2025-11-19T23:08:37Z</updated>
<author>
<name>Shikang Fan</name>
<email>shikang.fan@amd.com</email>
</author>
<published>2025-11-19T10:05:10Z</published>
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<id>urn:sha1:c156c7f27ecdb7b89dbbeaaa1f40d9fadc3c1680</id>
<content type='text'>
Add SRIOV check when setting VCN ring's supported reset mask.

Signed-off-by: Shikang Fan &lt;shikang.fan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit ee9b603ad43f9870eb75184f9fb0a84f8c3cc852)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/ttm: Fix crash when handling MMIO_REMAP in PDE flags</title>
<updated>2025-11-19T23:08:37Z</updated>
<author>
<name>Srinivasan Shanmugam</name>
<email>srinivasan.shanmugam@amd.com</email>
</author>
<published>2025-11-18T08:58:33Z</published>
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<id>urn:sha1:21f46f54769c45ac8ca0dbaa977bc1b436ffdee2</id>
<content type='text'>
The MMIO_REMAP BO is a special 4K IO page that does not have a ttm_tt
behind it. However, amdgpu_ttm_tt_pde_flags() was treating it like
normal TT/doorbell/preempt memory and unconditionally accessed
ttm-&gt;caching. For the MMIO_REMAP BO, ttm is NULL, so this leads to a
NULL pointer dereference when computing PDE flags.

Fix this by checking that ttm is non-NULL before reading ttm-&gt;caching.
This prevents the crash for MMIO_REMAP and also makes the code more
defensive if other BOs ever come through without a ttm_tt.

Fixes: fb5a52dbe9fe ("drm/amdgpu: Implement TTM handling for MMIO_REMAP placement")
Suggested-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Srinivasan Shanmugam &lt;srinivasan.shanmugam@amd.com&gt;
Reviewed-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Tested-by: Jesse Zhang &lt;Jesse.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 0db94da5a0a1cacda080b9ec8425fcbe4babc141)
</content>
</entry>
<entry>
<title>drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag</title>
<updated>2025-11-19T23:08:37Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-11-19T09:25:42Z</published>
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<id>urn:sha1:a44592339397bc6715917997c6869bdedd1a7256</id>
<content type='text'>
This fixes sparse mappings (aka. partially resident textures).

Check the correct flags.
Since a recent refactor, the code works with uAPI flags (for
mapping buffer objects), and not PTE (page table entry) flags.

Fixes: 6716a823d18d ("drm/amdgpu: rework how PTE flags are generated v3")
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 8feeab26c80635b802f72b3ed986c693ff8f3212)
</content>
</entry>
<entry>
<title>drm/amdgpu: Skip emit de meta data on gfx11 with rs64 enabled</title>
<updated>2025-11-19T23:08:37Z</updated>
<author>
<name>Yifan Zha</name>
<email>Yifan.Zha@amd.com</email>
</author>
<published>2025-11-14T09:48:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=80d8a9ad1587b64c545d515ab6cb7ecb9908e1b3'/>
<id>urn:sha1:80d8a9ad1587b64c545d515ab6cb7ecb9908e1b3</id>
<content type='text'>
[Why]
Accoreding to CP updated to RS64 on gfx11,
WRITE_DATA with PREEMPTION_META_MEMORY(dst_sel=8) is illegal for CP FW.
That packet is used for MCBP on F32 based system.
So it would lead to incorrect GRBM write and FW is not handling that
extra case correctly.

[How]
With gfx11 rs64 enabled, skip emit de meta data.

Signed-off-by: Yifan Zha &lt;Yifan.Zha@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 8366cd442d226463e673bed5d199df916f4ecbcf)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd: Skip power ungate during suspend for VPE</title>
<updated>2025-11-19T23:08:36Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2025-11-18T13:18:10Z</published>
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<id>urn:sha1:31ab31433c9bd2f255c48dc6cb9a99845c58b1e4</id>
<content type='text'>
During the suspend sequence VPE is already going to be power gated
as part of vpe_suspend().  It's unnecessary to call during calls to
amdgpu_device_set_pg_state().

It actually can expose a race condition with the firmware if s0i3
sequence starts as well.  Drop these calls.

Cc: Peyton.Lee@amd.com
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 2a6c826cfeedd7714611ac115371a959ead55bda)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/jpeg: Add parse_cs for JPEG5_0_1</title>
<updated>2025-11-12T03:51:49Z</updated>
<author>
<name>Sathishkumar S</name>
<email>sathishkumar.sundararaju@amd.com</email>
</author>
<published>2025-10-07T07:47:51Z</published>
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<id>urn:sha1:bbe3c115030da431c9ec843c18d5583e59482dd2</id>
<content type='text'>
enable parse_cs callback for JPEG5_0_1.

Signed-off-by: Sathishkumar S &lt;sathishkumar.sundararaju@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 547985579932c1de13f57f8bcf62cd9361b9d3d3)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Ensure isp_kernel_buffer_alloc() creates a new BO</title>
<updated>2025-11-12T03:51:27Z</updated>
<author>
<name>Sultan Alsawaf</name>
<email>sultan@kerneltoast.com</email>
</author>
<published>2025-11-07T18:07:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7132f7e025f9382157543dd86a62d161335b48b9'/>
<id>urn:sha1:7132f7e025f9382157543dd86a62d161335b48b9</id>
<content type='text'>
When the BO pointer provided to amdgpu_bo_create_kernel() points to
non-NULL, amdgpu_bo_create_kernel() takes it as a hint to pin that address
rather than allocate a new BO.

This functionality is never desired for allocating ISP buffers. A new BO
should always be created when isp_kernel_buffer_alloc() is called, per the
description for isp_kernel_buffer_alloc().

Ensure this by zeroing *bo right before the amdgpu_bo_create_kernel() call.

Fixes: 55d42f616976 ("drm/amd/amdgpu: Add helper functions for isp buffers")
Reviewed-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Reviewed-by: Pratap Nirujogi &lt;pratap.nirujogi@amd.com&gt;
Signed-off-by: Sultan Alsawaf &lt;sultan@kerneltoast.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 73c8c29baac7f0c7e703d92eba009008cbb5228e)
</content>
</entry>
</feed>
