<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-07-17T18:34:31Z</updated>
<entry>
<title>drm/amdkfd: Remove GWS from process during uninit</title>
<updated>2019-07-17T18:34:31Z</updated>
<author>
<name>Joseph Greathouse</name>
<email>Joseph.Greathouse@amd.com</email>
</author>
<published>2019-07-17T14:47:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6a5d4877544b9014c70533200ad4a5f9d6e005c5'/>
<id>urn:sha1:6a5d4877544b9014c70533200ad4a5f9d6e005c5</id>
<content type='text'>
If we shut down a process without having destroyed its GWS-using
queues, it is possible that GWS BO will still be in the process
BO list during the gpuvm destruction. This list should be empty
at that time, so we should remove the GWS allocation at the
process uninit point if it is still around.

Signed-off-by: Joseph Greathouse &lt;Joseph.Greathouse@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Return proper error code for gws alloc API</title>
<updated>2019-05-31T15:39:33Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-05-28T19:51:49Z</published>
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<id>urn:sha1:443e902eeef96f3bed54a7067c50a07f06074373</id>
<content type='text'>
Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Add function to set queue gws</title>
<updated>2019-05-28T19:44:24Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-05-07T02:31:52Z</published>
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<id>urn:sha1:eb82da1dc4429c026a165f419f8c76d7bbdcf26f</id>
<content type='text'>
Add functions in process queue manager to
set/unset queue gws. Also set process's number
of gws used. Currently only one queue in
process can use and use all gws.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Introduce XGMI SDMA queue type</title>
<updated>2019-05-24T17:21:02Z</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2019-02-07T20:02:27Z</published>
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<id>urn:sha1:1b4670f6983156526c286723465fdf805070b45d</id>
<content type='text'>
Existing QUEUE_TYPE_SDMA means PCIe optimized SDMA queues.
Introduce a new QUEUE_TYPE_SDMA_XGMI, which is optimized
for non-PCIe transfer such as XGMI.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Init mqd managers in device queue manager init</title>
<updated>2019-05-24T17:21:02Z</updated>
<author>
<name>Oak Zeng</name>
<email>ozeng@amd.com</email>
</author>
<published>2018-12-05T16:15:27Z</published>
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<id>urn:sha1:fdfa090bc90f34543b8efd05b05a143ae6d52406</id>
<content type='text'>
Previously mqd managers was initialized on demand. As there
are only a few type of mqd managers, the on demand initialization
doesn't save too much memory. Initialize them on device
queue initialization instead and delete the get_mqd_manager
interface. This makes codes more organized for future changes.

Signed-off-by: Oak Zeng &lt;ozeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Introduce DIQ type mqd manager</title>
<updated>2019-05-24T17:21:02Z</updated>
<author>
<name>Oak Zeng</name>
<email>ozeng@amd.com</email>
</author>
<published>2018-12-04T02:38:43Z</published>
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<id>urn:sha1:59f650a06f8f530e2412e5c47106cd8b8895bd89</id>
<content type='text'>
With introduction of new mqd allocation scheme for HIQ,
DIQ and HIQ use different mqd allocation scheme, DIQ
can't reuse HIQ mqd manager

Signed-off-by: Oak Zeng &lt;ozeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Add wavefront context save state retrieval ioctl</title>
<updated>2018-09-27T02:09:15Z</updated>
<author>
<name>Jay Cornwall</name>
<email>Jay.Cornwall@amd.com</email>
</author>
<published>2017-05-02T22:39:37Z</published>
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<id>urn:sha1:5df099e8bc83f4f3af8711ee0b9b8faef359ffff</id>
<content type='text'>
Wavefront context save data is of interest to userspace clients for
debugging static wavefront state. The MQD contains two parameters
required to parse the control stack and the control stack itself
is kept in the MQD from gfx9 onwards.

Add an ioctl to fetch the context save area and control stack offsets
and to copy the control stack to a userspace address if it is kept in
the MQD.

Signed-off-by: Jay Cornwall &lt;Jay.Cornwall@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Add CU-masking ioctl to KFD</title>
<updated>2018-07-14T23:05:59Z</updated>
<author>
<name>Felix Kuehling</name>
<email>Felix.Kuehling@amd.com</email>
</author>
<published>2018-07-14T23:05:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=39e7f331864d2b9e30d5f3fd2121e182b2c9c8a9'/>
<id>urn:sha1:39e7f331864d2b9e30d5f3fd2121e182b2c9c8a9</id>
<content type='text'>
CU-masking allows a KFD client to control the set of CUs used by a
user mode queue for executing compute dispatches. This can be used
for optimizing the partitioning of the GPU and minimize conflicts
between concurrent tasks.

Signed-off-by: Flora Cui &lt;flora.cui@amd.com&gt;
Signed-off-by: Kent Russell &lt;kent.russell@amd.com&gt;
Signed-off-by: Eric Huang &lt;JinHuiEric.Huang@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
Signed-off-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Make SDMA engine number an ASIC-dependent variable</title>
<updated>2018-07-13T20:17:44Z</updated>
<author>
<name>Yong Zhao</name>
<email>yong.zhao@amd.com</email>
</author>
<published>2018-07-13T20:17:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=98bb92222eef6ac022f352aa4224f4c94a119199'/>
<id>urn:sha1:98bb92222eef6ac022f352aa4224f4c94a119199</id>
<content type='text'>
On Raven there is only one SDMA engine instead of previously assumed two,
so we need to adapt our code to this new scenario.

Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Clean up reference of radeon</title>
<updated>2018-07-12T02:33:08Z</updated>
<author>
<name>Yong Zhao</name>
<email>yong.zhao@amd.com</email>
</author>
<published>2018-07-12T02:33:08Z</published>
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<id>urn:sha1:e7016d8e6f1b92888cc6093fd4e09d9f85934eb9</id>
<content type='text'>
Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
</content>
</entry>
</feed>
