<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-08-18T21:56:53Z</updated>
<entry>
<title>drm/amd/display: Fix Xorg desktop unresponsive on Replay panel</title>
<updated>2025-08-18T21:56:53Z</updated>
<author>
<name>Tom Chung</name>
<email>chiahsuan.chung@amd.com</email>
</author>
<published>2025-07-18T10:25:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=66af73a1c319336694a8610fe4c2943f7b33066c'/>
<id>urn:sha1:66af73a1c319336694a8610fe4c2943f7b33066c</id>
<content type='text'>
[WHY &amp; HOW]
IPS &amp; self-fresh feature can cause vblank counter resets between
vblank disable and enable.
It may cause system stuck due to wait the vblank counter.

Call the drm_crtc_vblank_restore() during vblank enable to estimate
missed vblanks by using timestamps and update the vblank counter in
DRM.

It can make the vblank counter increase smoothly and resolve this issue.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Sun peng (Leo) Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 34d66bc7ff10e146a4cec76cf286979740a10954)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Add primary plane to commits for correct VRR handling</title>
<updated>2025-08-04T19:43:58Z</updated>
<author>
<name>Michel Dänzer</name>
<email>mdaenzer@redhat.com</email>
</author>
<published>2025-07-30T08:09:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3477c1b0972dc1c8a46f78e8fb1fa6966095b5ec'/>
<id>urn:sha1:3477c1b0972dc1c8a46f78e8fb1fa6966095b5ec</id>
<content type='text'>
amdgpu_dm_commit_planes calls update_freesync_state_on_stream only for
the primary plane. If a commit affects a CRTC but not its primary plane,
it would previously not trigger a refresh cycle or affect LFC, violating
current UAPI semantics.

Fixes e.g. atomic commits affecting only the cursor plane being limited
to the minimum refresh rate.

Don't do this for the legacy cursor ioctls though, it would break the
UAPI semantics for those.

Suggested-by: Xaver Hugl &lt;xaver.hugl@kde.org&gt;
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3034
Signed-off-by: Michel Dänzer &lt;mdaenzer@redhat.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit cc7bfba95966251b254cb970c21627124da3b7f4)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Disable CRTC degamma LUT for DCN401</title>
<updated>2025-07-15T18:07:53Z</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2025-07-07T20:52:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=340231cdceec2c45995d773a358ca3c341f151aa'/>
<id>urn:sha1:340231cdceec2c45995d773a358ca3c341f151aa</id>
<content type='text'>
In DCN401 pre-blending degamma LUT isn't affecting cursor as in previous
DCN version. As this is not the behavior close to what is expected for
CRTC degamma LUT, disable CRTC degamma LUT property in this HW.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/4176
---

When enabling HDR on KDE, it takes the first CRTC 1D LUT available and
apply a color transformation (Gamma 2.2 -&gt; PQ). AMD driver usually
advertises a CRTC degamma LUT as the first CRTC 1D LUT, but it's
actually applied pre-blending. In previous HW version, it seems to work
fine because the 1D LUT was applied to cursor too, but DCN401 presents a
different behavior and the 1D LUT isn't affecting the hardware cursor.

To address the wrong gamma on cursor with HDR (see the link), I came up
with this patch that disables CRTC degamma LUT in this hw, since it
presents a different behavior than others. With this KDE sees CRTC
regamma LUT as the first post-blending 1D LUT available. This is
actually more consistent with AMD color pipeline. It was tested by the
reporter, since I don't have the HW available for local testing and
debugging.

Melissa
---

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amd/display: pause the workload setting in dm"</title>
<updated>2025-05-29T14:55:47Z</updated>
<author>
<name>Fangzhi Zuo</name>
<email>Jerry.Zuo@amd.com</email>
</author>
<published>2025-05-20T19:30:25Z</published>
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<id>urn:sha1:988b1d2164a1cbe56616a1ded0c877a3ae753558</id>
<content type='text'>
This reverts commit 50f29ead1f1ba48983b6c5e3813b15e497714f55.

Reason for revert: cause corruption on Dell U3224KB DP2 display.

Signed-off-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: pause the workload setting in dm</title>
<updated>2025-04-09T14:53:11Z</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2025-03-28T02:34:57Z</published>
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<id>urn:sha1:50f29ead1f1ba48983b6c5e3813b15e497714f55</id>
<content type='text'>
Pause the workload setting in dm when doing idle optimization

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit b23f81c442ac33af0c808b4bb26333b881669bb7)
</content>
</entry>
<entry>
<title>drm/amd/display: Do not enable Replay and PSR while VRR is on in amdgpu_dm_commit_planes()</title>
<updated>2025-04-07T18:32:36Z</updated>
<author>
<name>Tom Chung</name>
<email>chiahsuan.chung@amd.com</email>
</author>
<published>2025-03-19T08:31:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=69a46ce1f15b4391c128d581f6936750f9bfa052'/>
<id>urn:sha1:69a46ce1f15b4391c128d581f6936750f9bfa052</id>
<content type='text'>
[Why]
Replay and PSR will cause some video corruption while VRR is enabled.

[How]
Do not enable the Replay and PSR while VRR is active in
amdgpu_dm_enable_self_refresh().

Fixes: 67edb81d6e9a ("drm/amd/display: Disable replay and psr while VRR is enabled")
Reviewed-by: Sun peng Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Disable replay and psr while VRR is enabled</title>
<updated>2025-01-13T19:21:36Z</updated>
<author>
<name>Tom Chung</name>
<email>chiahsuan.chung@amd.com</email>
</author>
<published>2024-12-05T15:20:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=67edb81d6e9af43a0d58edf74630f82cfda4155d'/>
<id>urn:sha1:67edb81d6e9af43a0d58edf74630f82cfda4155d</id>
<content type='text'>
[Why]
Replay and PSR will cause some video corruption while VRR is enabled.

[How]
1. Disable the Replay and PSR while VRR is enabled.
2. Change the amdgpu_dm_crtc_vrr_active() parameter to const.
   Because the function will only read data from dm_crtc_state.

Reviewed-by: Sun peng Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit d7879340e987b3056b8ae39db255b6c19c170a0d)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Do not wait for PSR disable on vbl enable</title>
<updated>2025-01-10T18:40:47Z</updated>
<author>
<name>Leo Li</name>
<email>sunpeng.li@amd.com</email>
</author>
<published>2024-12-09T17:58:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ff2e4d874726c549130308b6b46aa0f8a34e04cb'/>
<id>urn:sha1:ff2e4d874726c549130308b6b46aa0f8a34e04cb</id>
<content type='text'>
[Why]

Outside of a modeset/link configuration change, we should not have to
wait for the panel to exit PSR. Depending on the panel and it's state,
it may take multiple frames for it to exit PSR. Therefore, waiting in
all scenarios may cause perceived stuttering, especially in combination
with faster vblank shutdown.

[How]

PSR1 disable is hooked up to the vblank enable event, and vice versa. In
case of vblank enable, do not wait for panel to exit PSR, but still wait
in all other cases.

We also avoid a call to unnecessarily change power_opts on disable -
this ends up sending another command to dmcub fw.

When testing against IGT, some crc tests like kms_plane_alpha_blend and
amd_hotplug were failing due to CRC timeouts. This was found to be
caused by the early return before HW has fully exited PSR1. Fix this by
first making sure we grab a vblank reference, then waiting for panel to
exit PSR1, before programming hw for CRC generation.

Fixes: 58a261bfc967 ("drm/amd/display: use a more lax vblank enable policy for older ASICs")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3743
Reviewed-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit aa6713fa2046f4c09bf3013dd1420ae15603ca6f)
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Fix Panel Replay not update screen correctly</title>
<updated>2024-11-08T16:45:30Z</updated>
<author>
<name>Tom Chung</name>
<email>chiahsuan.chung@amd.com</email>
</author>
<published>2024-10-29T09:28:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ca628f0eddd73adfccfcc06b2a55d915bca4a342'/>
<id>urn:sha1:ca628f0eddd73adfccfcc06b2a55d915bca4a342</id>
<content type='text'>
[Why]
In certain use case such as KDE login screen, there will be no atomic
commit while do the frame update.
If the Panel Replay enabled, it will cause the screen not updated and
looks like system hang.

[How]
Delay few atomic commits before enabled the Panel Replay just like PSR.

Fixes: be64336307a6c ("drm/amd/display: Re-enable panel replay feature")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3686
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3682
Tested-By: Corey Hickey &lt;bugfood-c@fatooh.org&gt;
Tested-By: James Courtier-Dutton &lt;james.dutton@gmail.com&gt;
Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Change some variable name of psr</title>
<updated>2024-11-08T16:45:29Z</updated>
<author>
<name>Tom Chung</name>
<email>chiahsuan.chung@amd.com</email>
</author>
<published>2024-10-29T07:38:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c7fafb7a46b38a11a19342d153f505749bf56f3e'/>
<id>urn:sha1:c7fafb7a46b38a11a19342d153f505749bf56f3e</id>
<content type='text'>
Panel Replay feature may also use the same variable with PSR.
Change the variable name and make it not specify for PSR.

Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
