<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c, branch v5.0</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.0</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.0'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-02-08T19:12:25Z</updated>
<entry>
<title>drm/amd/display: Expose connector VRR range via debugfs</title>
<updated>2019-02-08T19:12:25Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-01-24T17:06:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=727962f030c23422a01e8b22d0f463815fb15ec4'/>
<id>urn:sha1:727962f030c23422a01e8b22d0f463815fb15ec4</id>
<content type='text'>
[Why]
It's useful to know the min and max vrr range for IGT testing.

[How]
Expose the min and max vfreq for the connector via a debugfs file
on the connector, "vrr_range".

Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: dm/amdgpu: make dp phy debugfs for eDP</title>
<updated>2018-10-12T17:53:04Z</updated>
<author>
<name>hersen wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-10-04T13:28:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8c6259bedab1681382b7829b1e8fc4f12fc4a215'/>
<id>urn:sha1:8c6259bedab1681382b7829b1e8fc4f12fc4a215</id>
<content type='text'>
[WHY] dp debugfs file does not exist for eDP under
      /sys/kernel/debug/dri/0/eDP-1. the root is phy debugfs
      is created for dp connector only.
[HOW] for eDP connector, create phy debugfs too.

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: David Francis &lt;David.Francis@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix ptr_ret.cocci warnings</title>
<updated>2018-09-12T21:29:57Z</updated>
<author>
<name>kbuild test robot</name>
<email>fengguang.wu@intel.com</email>
</author>
<published>2018-09-12T00:59:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8901a65f080ad6f4d7c3ef9f23c6f3a0e3e194aa'/>
<id>urn:sha1:8901a65f080ad6f4d7c3ef9f23c6f3a0e3e194aa</id>
<content type='text'>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c:771:1-3: WARNING: PTR_ERR_OR_ZERO can be used

 Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR

Generated by: scripts/coccinelle/api/ptr_ret.cocci

Fixes: e498eb713604 ("drm/amd/display: Add support for hw_state logging via debugfs")
CC: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: kbuild test robot &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Support reading hw state from debugfs file</title>
<updated>2018-08-27T20:20:49Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2018-08-15T16:00:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=46659a83e4662ed92000ec13445b8c0ca96fd2cc'/>
<id>urn:sha1:46659a83e4662ed92000ec13445b8c0ca96fd2cc</id>
<content type='text'>
[Why]

Logging hardware state can be done by triggering a write to the
debugfs file. It would also be useful to be able to read the hardware
state from the debugfs file to be able to generate a clean log without
timestamps.

[How]

Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log

Threading is an obvious concern when dealing with multiple debugfs
operations and blocking on global state in dm or dc seems unfavorable.

Adding an extra parameter for the debugfs log context state is the
implementation done here. Existing code that made use of DTN_INFO
and its associated macros needed to be refactored to support this.

We don't know the size of the log in advance so it reallocates the
log string dynamically. Once the log has been generated it's copied
into the user supplied buffer for the debugfs. This allows for seeking
support but it's worth nothing that unlike triggering output via
dmesg the hardware state might change in-between reads if your buffer
size is too small.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Jordan Lazare &lt;Jordan.Lazare@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support for hw_state logging via debugfs</title>
<updated>2018-08-27T20:20:17Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2018-08-14T19:40:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e498eb7136042aa9a352b1039c678537f4694158'/>
<id>urn:sha1:e498eb7136042aa9a352b1039c678537f4694158</id>
<content type='text'>
[Why]

We have logging methods for printing hardware state for newer ASICs
but no way to trigger the log output.

[How]

Add support for triggering the output via writing to a debugfs file
entry. Log output currently goes into dmesg for convenience, but
accessing via a read should be possible later.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Jordan Lazare &lt;Jordan.Lazare@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dp debugfs allow link rate lane count greater than dp rx reported caps</title>
<updated>2018-07-13T19:51:53Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-06-27T17:03:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=245524d9b827e184de1a23aff24c7872fed04cdb'/>
<id>urn:sha1:245524d9b827e184de1a23aff24c7872fed04cdb</id>
<content type='text'>
[Why]
when hw team does phy parameters tuning, there is need to force dp
link rate or lane count grater than the values from dp receiver to
check dp tx. current debufs limit link rate, lane count no more
than rx caps.

[How] remove force settings less than rx caps check

v2: Fix typo in title

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Linux hook test pattern through debufs</title>
<updated>2018-07-13T19:50:16Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-06-22T17:06:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=53a599de5560b95bf76bc12d17b93406c33e9f75'/>
<id>urn:sha1:53a599de5560b95bf76bc12d17b93406c33e9f75</id>
<content type='text'>
bug fix: phy test PLTAT is special 80bit test pattern. The 80bit
data should be hard coded within driver so that user does not
need input the deata. previous driver does not have hard coded
80 bits pattern data for PLTPAT. Other than this PLTPAT, user
has to input 80 bits pattern data. In case user input less than
10 bytes data, un-input data byte will be filled by 0x00.

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Linux set/read lane settings through debugfs</title>
<updated>2018-07-13T19:49:36Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-06-15T14:32:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f8ac2cf78f276b4d9fc0bc6b90f5e3560caa11de'/>
<id>urn:sha1:f8ac2cf78f276b4d9fc0bc6b90f5e3560caa11de</id>
<content type='text'>
 function: get current DP PHY settings: voltage swing, pre-emphasis,
 post-cursor2 (defined by VESA DP specification)

 valid values:  voltage swing: 0,1,2,3  pre-emphasis : 0,1,2,3
 post cursor2 : 0,1,2,3

 debugfs file phy_setings is located at  /sys/kernel/debug/dri/0/DP-x

 there will be directories, like DP-1, DP-2,DP-3, etc. for DP display

 --- to figure out which DP-x is the display for DP to be check,
 cd DP-x
 ls -ll
 There should be debugfs file, like link_settings, phy_settings.
 cat link_settings
 from lane_count, link_rate to figure which DP-x is for display to be
 worked on

 --- to get current DP PHY settings,
 cat phy_settings

 --- to change DP PHY settings,
 echo &lt;voltage_swing&gt; &lt;pre-emphasis&gt; &lt;post_cursor2&gt; &gt; phy_settings

 for examle, to change voltage swing to 2, pre-emphasis to 3,
 post_cursor2 to 0,
 echo 2 3 0 &gt; phy_settings

 ---  to check if change be applied, get current phy settings by
 cat phy_settings

 ---  in case invalid values are set by user, like
 echo 1 4 0 &gt; phy_settings

 HW will NOT be programmed by these settings.

cat phy_settings will show the previous valid settings.

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: hook dp test pattern through debugfs</title>
<updated>2018-07-13T19:49:02Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-06-19T16:14:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0a1d56599b9bb58464a8bf1243191eb32b36b694'/>
<id>urn:sha1:0a1d56599b9bb58464a8bf1243191eb32b36b694</id>
<content type='text'>
 set PHY layer or Link layer test pattern
 PHY test pattern is used for PHY SI check.
 Link layer test will not affect PHY SI.

 - normal video mode
  0 = DP_TEST_PATTERN_VIDEO_MODE

 - PHY test pattern supported
  1 = DP_TEST_PATTERN_D102
  2 = DP_TEST_PATTERN_SYMBOL_ERROR
  3 = DP_TEST_PATTERN_PRBS7
  4 = DP_TEST_PATTERN_80BIT_CUSTOM
  5 = DP_TEST_PATTERN_CP2520_1
  6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
  7 = DP_TEST_PATTERN_CP2520_3

 - DP PHY Link Training Patterns
  8 = DP_TEST_PATTERN_TRAINING_PATTERN1
  9 = DP_TEST_PATTERN_TRAINING_PATTERN2
  0xa = DP_TEST_PATTERN_TRAINING_PATTERN3
  0xb = DP_TEST_PATTERN_TRAINING_PATTERN4

 - DP Link Layer Test pattern
  0xc = DP_TEST_PATTERN_COLOR_SQUARES
  0xd = DP_TEST_PATTERN_COLOR_SQUARES_CEA
  0xe = DP_TEST_PATTERN_VERTICAL_BARS
  0xf = DP_TEST_PATTERN_HORIZONTAL_BARS
  0x10= DP_TEST_PATTERN_COLOR_RAMP

 debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x

 --- set test pattern
  echo &lt;test pattern #&gt; &gt; test_pattern

 - custom test pattern
  If test pattern # is not supported, NO HW programming will be done
  for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
  for the user pattern. input 10 bytes data are separated by space

  echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa &gt;
  test_pattern

 --- reset test pattern
  echo 0 &gt; test_pattern

 --- HPD detection is disabled when set PHY test pattern

  when PHY test pattern (pattern # within [1,7]) is set, HPD pin of
  HW ASIC is disable. User could unplug DP display from DP connected
  and plug scope to check test pattern PHY SI.
  If there is need unplug scope and plug DP display back, do steps
  below:
  echo 0 &gt; phy_test_pattern
  unplug scope
  plug DP display.

  "echo 0 &gt; phy_test_pattern" will re-enable HPD pin again so that
  video sw driver could detect "unplug scope" and "plug DP display"

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: set-read link rate and lane count through debugfs</title>
<updated>2018-07-13T19:47:45Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2018-06-15T18:25:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=41db5f1931ec73f2d909752e09ffb691fecdaaa1'/>
<id>urn:sha1:41db5f1931ec73f2d909752e09ffb691fecdaaa1</id>
<content type='text'>
 function description
 get/ set DP configuration: lane_count, link_rate, spread_spectrum

  valid lane count value: 1, 2, 4
  valid link rate value:
  06h = 1.62Gbps per lane
  0Ah = 2.7Gbps per lane
  0Ch = 3.24Gbps per lane
  14h = 5.4Gbps per lane
  1Eh = 8.1Gbps per lane

  debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings

  --- to get dp configuration

  xxd -l 300 phy_settings

  It will list current, verified, reported, preferred dp configuration.
  current -- for current video mode
  verified --- maximum configuration which pass link training
  reported --- DP rx report caps (DPCD register offset 0, 1 2)
  preferred --- user force settings

  --- set (or force) dp configuration

  echo &lt;lane_count&gt;  &lt;link_rate&gt;

  for example, to force to  2 lane, 2.7GHz,
  echo 4 0xa &gt; link_settings

  spread_spectrum could not be changed dynamically.

  in case invalid lane count, link rate are force, no hw programming will be
  done. please check link settings after force operation to see if HW get
  programming.

  xxd -l 300 link_settings

  check current and preferred settings.

Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
