linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c, branch v6.4

drm/amd/display: Pass DSC slice height to PSR FW

2023-01-24T18:26:25Z

[Why] When DSC is enabled, the PSRSU seletive update region must be multiple number of DSC slice height number. The original solution is to overwrite the SU Y granularity by DSC slice height in DAL driver. However, the size of the SU Y granularity variable only has 8 bytes and the DSC slice height may over the 8 bytes size. [How] Instead of overwriting the SU Y granularity value, add a new DSC slice height pararmeter and pass it to DMUB PSRSU FW. The PSRSU FW will refer to the DSC slice height value and extend the SU region. Reviewed-by: Dennis Chan Reviewed-by: ChunTao Tso Acked-by: Alan Liu Signed-off-by: Robin Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix PSR-SU/DSC interoperability support

2023-01-09T22:02:18Z

Currently, there are issues with enabling PSR-SU + DSC. This stems from the fact that DSC imposes a slice height on transmitted video data and we are not conforming to that slice height in PSR-SU regions. So, pass slice_height into su_y_granularity to feed the DSC slice height into PSR-SU code. Acked-by: Harry Wentland Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: explicitly disable psr_feature_enable appropriately

2022-10-10T21:09:30Z

[Why] If psr_feature_enable is set to true by default, it continues to be enabled for non capable links. [How] explicitly disable the feature on links that are not capable of the same. Fixes: 8c322309e48e9 ("drm/amd/display: Enable PSR") Signed-off-by: Shirish S Reviewed-by: Leo Li Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 5.15+

drm/amd/display: Prevent OTG shutdown during PSR SU

2022-09-29T13:42:42Z

[Why] Enabling Z10 optimizations allows DMUB to disable the OTG during PSR link-off. This theoretically saves power by putting more of the display hardware to sleep. However, we observe that with PSR SU, it causes visual artifacts, higher power usage, and potential system hang. This is partly due to an odd behavior with the VStartup interrupt used to signal DRM vblank events. If the OTG is toggled on/off during a PSR link on/off cycle, the vstartup interrupt fires twice in quick succession. This generates incorrectly timed vblank events. Additionally, it can cause cursor updates to generate visual artifacts. Note that this is not observed with PSR1 since PSR is fully disabled when there are vblank event requestors. Cursor updates are also artifact-free, likely because there are no selectively-updated (SU) frames that can generate artifacts. [How] A potential solution is to disable z10 idle optimizations only when fast updates (flips & cursor updates) are committed. A mechanism to do so would require some thoughtful design. Let's just disable idle optimizations for PSR2 for now. Fixes: 7cc191ee7621 ("drm/amd/display: Implement MPO PSR SU") Reported-by: August Wikerfors Link: https://lore.kernel.org/r/c1f8886a-5624-8f49-31b1-e42b6d20dcf5@augustwikerfors.se/ Tested-by: August Wikerfors Reviewed-by: Harry Wentland Signed-off-by: Leo Li Signed-off-by: Alex Deucher

drm/amd/display: Implement MPO PSR SU

2022-06-06T18:42:59Z

[WHY] For additional power savings, PSR SU (also referred to as PSR2) can be enabled on eDP panels with PSR SU support. PSR2 saves more power compared to PSR1 by allowing more opportunities for the display hardware to be shut down. In comparison to PSR1, Shut down can now occur in-between frames, as well as in display regions where there is no visible update. In otherwords, it allows for some display hw components to be enabled only for a **selectively updated** region of the visible display. Hence PSR SU. [HOW] To define the SU region, support from the OS is required. OS needs to inform driver of damaged regions that need to be flushed to the eDP panel. Today, such support is lacking in most compositors. Therefore, an in-between solution is to implement PSR SU for MPO and cursor scenarios. The plane bounds can be used to define the damaged region to be flushed to panel. This is achieved by: * Leveraging dm_crtc_state->mpo_requested flag to identify when MPO is enabled. * If MPO is enabled, only add updated plane bounds to dirty region. Determine plane update by either: * Existence of drm damaged clips attached to the plane (added by a damage-aware compositor) * Change in fb id (flip) * Change in plane bounds (position and dimensions) * If cursor is enabled, the old_pos and new_pos of cursor plus cursor size is used as damaged regions(*). (*) Cursor updates follow a different code path through DC. PSR SU for cursor is already implemented in DC, and the only thing required to enable is to set DC_PSR_VERSION_SU_1 on the eDP link. See dcn10_dmub_update_cursor_data(). Signed-off-by: Leo Li Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: calculate psr config settings in runtime in DM

2022-06-06T18:42:40Z

[why] Currently the psr configuration parameters are hardcoded before feeding into the DC helper before passing to DMUB FW. We'd rework to call a shared helper to calculate/update generic psr config fields which are relying on the stream timing and eDP sink PSR caps to avoid hard-coding. [how] - drop part of hard-coded psr config fields by replacing w/ the call of helper from DM before feeding into DC link setup psr helper - For those DM specific psr config fields, e.g. allow smu opt, is not to be set/updated from the shared helper but to rely on the DC feature mask - for the psr version field in psr_config structure, since only the field psr_version of DC link psr_settings matters for that fed to DMUB FW, thus no need to set/update the psr_version field of psr_config structure. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in amdgpu_dm

2022-05-10T21:53:13Z

[Why & How] CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC code should be OS-agnostic. This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN in amdgpu_dm directory. Reviewed-by: Rodrigo Siqueira Acked-by: Stylon Wang Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: implement shared PSR-SU sink validation helper

2022-04-13T13:14:22Z

[why] creating a generic helper for AMD specific PSR-SU sink validation. Moving the function to the power module to reference it across all OS. [how] - drop PSRSU specific sink validation helper and move to power module by reading PSR version and other PSR caps - call the new helper from linux DM (amdgpu_dm_psr) Acked-by: Pavle Kotarac Acked-by: Tom Chung Signed-off-by: David Zhang Signed-off-by: Alex Deucher

drm/amd/display: Refactor PSR DPCD caps detection

2022-02-23T19:22:03Z

[Why] To move the PSR DPCD caps detection into detect_edp_sink_caps() Reviewed-by: Anthony Koo Acked-by: Solomon Chiu Signed-off-by: Po Ting Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Use PSR version selected during set_psr_caps

2022-01-25T23:00:35Z

[Why] If the DPCD caps specifies a PSR version newer than PSR_VERSION_1 then we fallback to using PSR_VERSION_1 in amdgpu_dm_set_psr_caps. This gets overriden with the raw DPCD value in amdgpu_dm_link_setup_psr, which can result in DMCUB hanging if we pass in an unsupported PSR version number. [How] Fix the hang by using link->psr_settings.psr_version directly during amdgpu_dm_link_setup_psr. Tested-by: Daniel Wheeler Reviewed-by: Anthony Koo Acked-by: Rodrigo Siqueira Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher