<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/amdgpu_dm, branch v5.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-08-21T22:33:32Z</updated>
<entry>
<title>drm/amd/display: Calculate bpc based on max_requested_bpc</title>
<updated>2019-08-21T22:33:32Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-08-21T15:27:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ec6e491353b9024d4b1a65c48b21e3bc0faeae4e'/>
<id>urn:sha1:ec6e491353b9024d4b1a65c48b21e3bc0faeae4e</id>
<content type='text'>
[Why]
The only place where state-&gt;max_bpc is updated on the connector is
at the start of atomic check during drm_atomic_connector_check. It
isn't updated when adding the connectors to the atomic state after
the fact. It also doesn't necessarily reflect the right value when
called in amdgpu during mode validation outside of atomic check.

This can cause the wrong bpc to be used even if the max_requested_bpc
is the correct value.

[How]
Don't rely on state-&gt;max_bpc reflecting the real bpc value and just
do the min(...) based on display info bpc and max_requested_bpc.

Fixes: 01933ba42d3d ("drm/amd/display: Use current connector state if NULL when checking bpc")
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Force uclk to max for every state</title>
<updated>2019-07-18T19:11:47Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-07-05T20:54:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=02316e963a5a2217aa13f64bb5fc37a3a6d0f5ef'/>
<id>urn:sha1:02316e963a5a2217aa13f64bb5fc37a3a6d0f5ef</id>
<content type='text'>
Workaround for now to avoid underflow.

The uclk switch time should really be bumped up to 404, but doing so
would expose p-state hang issues for higher bandwidth display
configurations.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Print out voltage in DM_PPLIB</title>
<updated>2019-07-12T03:04:22Z</updated>
<author>
<name>Paul Menzel</name>
<email>pmenzel@molgen.mpg.de</email>
</author>
<published>2019-07-08T11:50:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5f0f531c4f8a97258dd3133db74926574e6373ab'/>
<id>urn:sha1:5f0f531c4f8a97258dd3133db74926574e6373ab</id>
<content type='text'>
As the clock is already logged, also log the voltage.

Signed-off-by: Paul Menzel &lt;pmenzel@molgen.mpg.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add drm_audio_component support to amdgpu_dm</title>
<updated>2019-07-11T19:37:24Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-07-11T19:31:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6ce8f316673f61416738e6df7329ca508a607762'/>
<id>urn:sha1:6ce8f316673f61416738e6df7329ca508a607762</id>
<content type='text'>
[Why]
The drm_audio_component can be used to give pin ELD notifications
directly to the sound driver. This fixes audio endpoints disappearing
due to missing unsolicited notifications.

[How]
Send the notification via the audio component whenever we enable or
disable audio state on a stream. This matches what i915 does with
their drm_audio_component and what Takashi Iwai's proposed hack for
radeon/amdpgu did.

This is a bit delayed in when the notification actually occurs, however.
We wait until after all the programming is complete rather than sending
the notification mid sequence.

Particular care is needed for the get ELD callback since it can happen
outside the locking and fencing DRM does for atomic commits.

Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Takashi Iwai &lt;tiwai@suse.de&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fix interrupt client id for navi</title>
<updated>2019-07-02T20:46:24Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-07-02T16:39:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=843747253b427a579b360850e133f700b8bb5e0c'/>
<id>urn:sha1:843747253b427a579b360850e133f700b8bb5e0c</id>
<content type='text'>
All asics newer than vega10 use client ids, so simplify the
check.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Check stream in amdgpu_dm_commit_planes</title>
<updated>2019-06-25T18:23:43Z</updated>
<author>
<name>Ernst Sjöstrand</name>
<email>ernstp@gmail.com</email>
</author>
<published>2019-06-24T15:15:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ed9656fbc8b5b13a2350d9a7eb70f1b8d55e5803'/>
<id>urn:sha1:ed9656fbc8b5b13a2350d9a7eb70f1b8d55e5803</id>
<content type='text'>
Reported by smatch:
amdgpu_dm.c:5637 amdgpu_dm_commit_planes() error: we previously assumed 'acrtc_state-&gt;stream' could be null
This seems to be checked for null pretty consistently elsewhere.

Signed-off-by: Ernst Sjöstrand &lt;ernstp@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'drm-next' into drm-next-5.3</title>
<updated>2019-06-25T13:42:25Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-06-25T13:42:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d7929c1e13e3788e7cb741d75b5baec5e53eff21'/>
<id>urn:sha1:d7929c1e13e3788e7cb741d75b5baec5e53eff21</id>
<content type='text'>
Backmerge drm-next and fix up conflicts due to drmP.h removal.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rework CRTC color management</title>
<updated>2019-06-22T14:34:13Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-05-09T16:14:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cf020d49b3c4ef6ab6f26be3dbf2f36b3df9f797'/>
<id>urn:sha1:cf020d49b3c4ef6ab6f26be3dbf2f36b3df9f797</id>
<content type='text'>
[Why]
To prepare for the upcoming DRM plane color management properties
we need to correct a lot of wrong behavior and assumptions made for
CRTC color management.

The documentation added by this commit in amdgpu_dm_color explains
how the HW color pipeline works and its limitations with the DRM
interface.

The current implementation does the following wrong:
- Implicit sRGB DGM when no CRTC DGM is set
- Implicit sRGB RGM when no CRTC RGM is set
- No way to specify a non-linear DGM matrix that produces correct output
- No way to specify a correct RGM when a linear DGM is used

We had workarounds for passing kms_color tests but not all of the
behavior we had wrong was covered by these tests (especially when
it comes to non-linear DGM). Testing both DGM and RGM at the same time
isn't something kms_color tests well either.

[How]
The specifics for how color management works in AMDGPU and the new
behavior can be found by reading the documentation added to
amdgpu_dm_color.c from this patch.

All of the incorrect cases from the old implementation have been
addressed for the atomic interface, but there still a few TODOs for
the legacy one.

Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.

The result looks correct from visual inspection but the CRC no longer
matches. For reference, the test was previously doing the following:

linear degamma -&gt; CTM -&gt; sRGB regamma -&gt; RGB to YUV (709) -&gt; ...

Now the test is doing:

linear degamma -&gt; CTM -&gt; linear regamma -&gt; RGB to YUV (709) -&gt; ...

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Sun peng Li &lt;Sunpeng.Li@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy</title>
<updated>2019-06-22T14:34:13Z</updated>
<author>
<name>Wenjing Liu</name>
<email>Wenjing.Liu@amd.com</email>
</author>
<published>2019-05-16T17:01:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=39a4eb853f9ac85e9b042874ef5fa12c8e20e440'/>
<id>urn:sha1:39a4eb853f9ac85e9b042874ef5fa12c8e20e440</id>
<content type='text'>
[why]
Current policy assumes virtual DPCD peer device as
an individual MST branch device with 1 input and 1 output.
However this is only true for virtual DP-to-DP peer device.
In general there are three types of virtual DP peer devices.
1. Sink peer device with virtual DPCD.
2. Virtual DP-to-DP Peer device with virtual DPCD.
3. Virtual DP-to-HDMI Protocol Converter Peer Device with
Virtual DPCD.
So we should break the assumption and handle all three types.

[how]
DP-to-DP peer device will have virtual DPCD cap upstream.
Sink peer device will have virtual DPCD on the logical port.
Dp to HDMI protocol converter peer device will have virtual DPCD
on its converter port.
For DSC capable Synaptics non VGA port we workaround by enumerating
a virutal DPCD peer device on its upstream
even if it doesn't have one.

Signed-off-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add power down display on boot flag</title>
<updated>2019-06-22T14:34:10Z</updated>
<author>
<name>Thomas Lim</name>
<email>Thomas.Lim@amd.com</email>
</author>
<published>2019-05-07T20:08:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=78ad75f8d77a1a5dd99d8d8dae66c49113bd0bd7'/>
<id>urn:sha1:78ad75f8d77a1a5dd99d8d8dae66c49113bd0bd7</id>
<content type='text'>
[Why]
Due to the generic introduction of seamless boot, the display is no
longer blanked upon boot. However, this causes corruption on some
systems that does not lock the memory in the non-secure boot case,
resulting in brief corruption on boot due to garbage being written into
the frame buffer.

[How]
Add a flag, read during DC init, to determine whether display should be
blanked on boot. Default to true.

Signed-off-by: Thomas Lim &lt;Thomas.Lim@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
