<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/amdgpu_dm, branch v6.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2024-01-04T14:48:15Z</updated>
<entry>
<title>drm/amd/display: Fix sending VSC (+ colorimetry) packets for DP/eDP displays without PSR</title>
<updated>2024-01-04T14:48:15Z</updated>
<author>
<name>Joshua Ashton</name>
<email>joshua@froggi.es</email>
</author>
<published>2024-01-01T18:28:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=202260f64519e591b5cd99626e441b6559f571a3'/>
<id>urn:sha1:202260f64519e591b5cd99626e441b6559f571a3</id>
<content type='text'>
The check for sending the vsc infopacket to the display was gated behind
PSR (Panel Self Refresh) being enabled.

The vsc infopacket also contains the colorimetry (specifically the
container color gamut) information for the stream on modern DP.

PSR is typically only supported on mobile phone eDP displays, thus this
was not getting sent for typical desktop monitors or TV screens.

This functionality is needed for proper HDR10 functionality on DP as it
wants BT2020 RGB/YCbCr for the container color space.

Cc: stable@vger.kernel.org
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Xaver Hugl &lt;xaver.hugl@gmail.com&gt;
Cc: Melissa Wen &lt;mwen@igalia.com&gt;
Fixes: 15f9dfd545a1 ("drm/amd/display: Register Colorspace property for DP and HDMI")
Tested-by: Simon Berz &lt;simon@berz.me&gt;
Tested-by: Xaver Hugl &lt;xaver.hugl@kde.org&gt;
Signed-off-by: Joshua Ashton &lt;joshua@froggi.es&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: pbn_div need be updated for hotplug event</title>
<updated>2024-01-03T23:56:48Z</updated>
<author>
<name>Wayne Lin</name>
<email>wayne.lin@amd.com</email>
</author>
<published>2023-12-04T02:09:33Z</published>
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<id>urn:sha1:9cdef4f720376ef0fb0febce1ed2377c19e531f9</id>
<content type='text'>
link_rate sometime will be changed when DP MST connector hotplug, so
pbn_div also need be updated; otherwise, it will mismatch with
link_rate, causes no output in external monitor.

This is a backport to 6.7 and older.

Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Jerry Zuo &lt;jerry.zuo@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Wade Wang &lt;wade.wang@hp.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix hw rotated modes when PSR-SU is enabled</title>
<updated>2023-12-11T17:41:05Z</updated>
<author>
<name>Hamza Mahfooz</name>
<email>hamza.mahfooz@amd.com</email>
</author>
<published>2023-12-05T19:55:04Z</published>
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<id>urn:sha1:f528ee145bd0076cd0ed7e7b2d435893e6329e98</id>
<content type='text'>
We currently don't support dirty rectangles on hardware rotated modes.
So, if a user is using hardware rotated modes with PSR-SU enabled,
use PSR-SU FFU for all rotated planes (including cursor planes).

Cc: stable@vger.kernel.org
Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support")
Reported-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2952
Tested-by: Kai-Heng Feng &lt;kai.heng.feng@canonical.com&gt;
Tested-by: Bin Li &lt;binli@gnome.org&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add monitor patch for specific eDP</title>
<updated>2023-12-06T20:59:17Z</updated>
<author>
<name>Ivan Lipski</name>
<email>ivlipski@amd.com</email>
</author>
<published>2023-12-01T13:25:16Z</published>
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<id>urn:sha1:3d71a8726e05a35beb9de394e86ce896d69e563f</id>
<content type='text'>
[WHY]
Some eDP panels's ext caps don't write initial value cause the value of
dpcd_addr(0x317) is random.  It means that sometimes the eDP will
clarify it is OLED, miniLED...etc cause the backlight control interface
is incorrect.

[HOW]
Add a new panel patch to remove sink ext caps(HDR,OLED...etc)

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Sun peng Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivlipski@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix ABM disablement</title>
<updated>2023-11-29T23:08:24Z</updated>
<author>
<name>Hamza Mahfooz</name>
<email>hamza.mahfooz@amd.com</email>
</author>
<published>2023-11-22T19:50:34Z</published>
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<id>urn:sha1:b9f46f0b98784e40288ee393f863f553fde062fa</id>
<content type='text'>
On recent versions of DMUB firmware, if we want to completely disable
ABM we have to pass ABM_LEVEL_IMMEDIATE_DISABLE as the requested ABM
level to DMUB. Otherwise, LCD eDP displays are unable to reach their
maximum brightness levels. So, to fix this whenever the user requests an
ABM level of 0 pass ABM_LEVEL_IMMEDIATE_DISABLE to DMUB instead. Also,
to keep the user's experience consistent map ABM_LEVEL_IMMEDIATE_DISABLE
to 0 when a user tries to read the requested ABM level.

Cc: stable@vger.kernel.org # 6.1+
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox</title>
<updated>2023-11-17T05:54:58Z</updated>
<author>
<name>Lewis Huang</name>
<email>lewis.huang@amd.com</email>
</author>
<published>2023-10-19T09:22:21Z</published>
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<id>urn:sha1:5911d02cac70d7fb52009fbd37423e63f8f6f9bc</id>
<content type='text'>
[WHY]
Flush command sent to DMCUB spends more time for execution on
a dGPU than on an APU. This causes cursor lag when using high
refresh rate mouses.

[HOW]
1. Change the DMCUB mailbox memory location from FB to inbox.
2. Only change windows memory to inbox.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Lewis Huang &lt;lewis.huang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable fast plane updates on DCN3.2 and above</title>
<updated>2023-11-17T05:50:57Z</updated>
<author>
<name>Tianci Yin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2023-11-01T01:47:13Z</published>
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<id>urn:sha1:435f5b369657cffee4b04db1f5805b48599f4dbe</id>
<content type='text'>
[WHY]
When cursor moves across screen boarder, lag cursor observed,
since subvp settings need to sync up with vblank that causes
cursor updates being delayed.

[HOW]
Enable fast plane updates on DCN3.2 to fix it.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Tianci Yin &lt;tianci.yin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix NULL dereference</title>
<updated>2023-11-17T05:50:33Z</updated>
<author>
<name>José Pekkarinen</name>
<email>jose.pekkarinen@foxhound.fi</email>
</author>
<published>2023-11-14T15:27:51Z</published>
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<id>urn:sha1:270b301beca58e427a0fda7523a71a9562e644bb</id>
<content type='text'>
The following patch will fix a minor issue where a debug message is
referencing an struct that has just being checked whether is null or
not. This has been noticed by using coccinelle, in the following output:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c:540:25-29: ERROR: aconnector is NULL but dereferenced.

Fixes: 5d72e247e58c ("drm/amd/display: switch DC over to the new DRM logging macros")
Signed-off-by: José Pekkarinen &lt;jose.pekkarinen@foxhound.fi&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix a NULL pointer dereference in amdgpu_dm_i2c_xfer()</title>
<updated>2023-11-17T05:50:15Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-11-08T19:31:57Z</published>
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<id>urn:sha1:b71f4ade1b8900d30c661d6c27f87c35214c398c</id>
<content type='text'>
When ddc_service_construct() is called, it explicitly checks both the
link type and whether there is something on the link which will
dictate whether the pin is marked as hw_supported.

If the pin isn't set or the link is not set (such as from
unloading/reloading amdgpu in an IGT test) then fail the
amdgpu_dm_i2c_xfer() call.

Cc: stable@vger.kernel.org
Fixes: 22676bc500c2 ("drm/amd/display: Fix dmub soft hang for PSR 1")
Link: https://github.com/fwupd/fwupd/issues/6327
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix DSC not Enabled on Direct MST Sink</title>
<updated>2023-11-17T05:48:02Z</updated>
<author>
<name>Fangzhi Zuo</name>
<email>jerry.zuo@amd.com</email>
</author>
<published>2023-10-23T17:57:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a58555359a9f870543aaddef277c3396159895ce'/>
<id>urn:sha1:a58555359a9f870543aaddef277c3396159895ce</id>
<content type='text'>
[WHY &amp; HOW]
For the scenario when a dsc capable MST sink device is directly
connected, it needs to use max dsc compression as the link bw constraint.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Roman Li &lt;roman.li@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;jerry.zuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
