<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c, branch v6.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-04-21T15:26:59Z</updated>
<entry>
<title>drm/amd/display: To apply the adjusted DP ref clock for DP devices</title>
<updated>2025-04-21T15:26:59Z</updated>
<author>
<name>Yiling Chen</name>
<email>yi-ling.chen2@amd.com</email>
</author>
<published>2025-03-04T08:52:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f53d0f48a89ccf13a1598985ab1782ec105cb049'/>
<id>urn:sha1:f53d0f48a89ccf13a1598985ab1782ec105cb049</id>
<content type='text'>
[Why]
For some pixel clock margin sensitive external monitor,
we could not keep original DP ref clock for the ASICs
supported SSC DP ref clock.

[How]
From slicon design team's comment,
we have to apply the adjusted DP ref clock for
DP devices.
DP 128b (DP2) signals uses the DTBCLK not DP ref.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Yiling Chen &lt;yi-ling.chen2@amd.com&gt;
Signed-off-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Block Invalid TMDS operation</title>
<updated>2024-12-18T17:21:37Z</updated>
<author>
<name>Chris Park</name>
<email>chris.park@amd.com</email>
</author>
<published>2024-12-03T19:33:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=95265e4b2b3a9e47b40ffaa6587f335e4aa0b549'/>
<id>urn:sha1:95265e4b2b3a9e47b40ffaa6587f335e4aa0b549</id>
<content type='text'>
[Why]
When sink type is TMDS, PHY programming does not block against pixel
clock greater than 600MHz.

[How]
Based on sink type, block greater than 600MHz phy programming.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Chris Park &lt;chris.park@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix possible overflow in integer multiplication</title>
<updated>2024-07-01T20:06:53Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2024-06-08T04:09:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bbd0d1c942cbac87404ed2bca0aa4f7907b8f47f'/>
<id>urn:sha1:bbd0d1c942cbac87404ed2bca0aa4f7907b8f47f</id>
<content type='text'>
[WHAT &amp; HOW]
Integer multiplies integer may overflow in context that expects an
expression of unsigned/siged long long (64 bits). This can be fixed
by casting integer to unsigned/siged long long to force 64 bits results.

This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Jerry Zuo &lt;jerry.zuo@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Prevent overflow on DTO calculation</title>
<updated>2024-06-14T20:17:15Z</updated>
<author>
<name>Chris Park</name>
<email>chris.park@amd.com</email>
</author>
<published>2024-05-28T01:21:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8362061eed6761a36866876ba2dd00ec638a13b4'/>
<id>urn:sha1:8362061eed6761a36866876ba2dd00ec638a13b4</id>
<content type='text'>
[Why]
uint32_t is implicitly converted to uint64_t while multiplication
still happens on uint32_t side.  This creates digit overflow
for large pixel clock which is meant to be retained in uint64_t.

[How]
Calculate multiplication of units in uint64_t domain instead of
uint32_t in DTO parameter clock caculation.

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Acked-by: Zaeem Mohamed &lt;zaeem.mohamed@amd.com&gt;
Signed-off-by: Chris Park &lt;chris.park@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Modify HPO pixel clock programming to support DPM</title>
<updated>2024-05-20T20:20:24Z</updated>
<author>
<name>Dillon Varone</name>
<email>dillon.varone@amd.com</email>
</author>
<published>2024-03-14T20:21:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7991585b7743fb9b88e8cd2317ce7a87c4f86450'/>
<id>urn:sha1:7991585b7743fb9b88e8cd2317ce7a87c4f86450</id>
<content type='text'>
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to
hardware guidance.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Use the correct TMDS function to avoid DVI issues</title>
<updated>2024-05-20T20:19:34Z</updated>
<author>
<name>Chris Park</name>
<email>chris.park@amd.com</email>
</author>
<published>2024-04-02T06:06:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7f46daca139985cbfb79f1c3a41f4df065d45b1e'/>
<id>urn:sha1:7f46daca139985cbfb79f1c3a41f4df065d45b1e</id>
<content type='text'>
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.

[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Chris Park &lt;chris.park@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add misc DC changes for DCN401</title>
<updated>2024-04-26T21:23:34Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2024-03-20T17:56:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=00c391102abc13763e2bfc90e05503109b19f074'/>
<id>urn:sha1:00c391102abc13763e2bfc90e05503109b19f074</id>
<content type='text'>
Add miscellaneous changes to enable DCN401 init

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Adjust dprefclk by down spread percentage.</title>
<updated>2024-04-10T02:16:45Z</updated>
<author>
<name>Zhongwei</name>
<email>zhongwei.zhang@amd.com</email>
</author>
<published>2024-03-27T05:49:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=364b1c1de6de36c1b28690265c904c682aecc266'/>
<id>urn:sha1:364b1c1de6de36c1b28690265c904c682aecc266</id>
<content type='text'>
[Why]
OLED panels show no display for large vtotal timings.

[How]
Check if ss is enabled and read from lut for spread spectrum percentage.
Adjust dprefclk as required. DP_DTO adjustment is for edp only.

Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Zhongwei &lt;zhongwei.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: To adjust dprefclk by down spread percentage</title>
<updated>2024-01-09T20:43:53Z</updated>
<author>
<name>Martin Tsai</name>
<email>martin.tsai@amd.com</email>
</author>
<published>2023-12-18T08:36:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=17e74e11ac2b46e7514705ae7abfb93ac0e20bd6'/>
<id>urn:sha1:17e74e11ac2b46e7514705ae7abfb93ac0e20bd6</id>
<content type='text'>
[Why]
Panels show corruption with high refresh rate timings when ssc is
enabled.

[How]
Read down-spread percentage from lut to adjust dprefclk. Issues come
from S0i3 with this commit has been fixed by SMU.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Martin Tsai &lt;martin.tsai@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: switch DC over to the new DRM logging macros</title>
<updated>2023-09-26T21:00:21Z</updated>
<author>
<name>Hamza Mahfooz</name>
<email>hamza.mahfooz@amd.com</email>
</author>
<published>2023-09-20T17:38:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5d72e247e58c966f4e50cffebf0d414de7fc90ed'/>
<id>urn:sha1:5d72e247e58c966f4e50cffebf0d414de7fc90ed</id>
<content type='text'>
For multi-GPU systems it is difficult to tell which GPU a particular
message is being printed for and that is undesirable because it
complicates debugging efforts. Also, the new macros allow us to enable
logging for particular parts of the codebase more selectively (since we
no longer need to throw everything at DRM_DEBUG_KMS()). So, for the
reasons outlined above we should switch to the new macros.

We can accomplish this by using the existing DC_LOGGER code to pass
around the relevant `struct drm_device` which will be fed to the new
macros in logger_types.h. Also, we must get rid of all instances of the
DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use
the DC logger there and we can simply refer to the macros directly
there instead.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
