<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c, branch v5.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-09-14T19:57:09Z</updated>
<entry>
<title>drm/amd/display: Add DPCD writes at key points</title>
<updated>2021-09-14T19:57:09Z</updated>
<author>
<name>Leo (Hanghong) Ma</name>
<email>hanghong.ma@amd.com</email>
</author>
<published>2021-08-15T18:17:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3550d6225b1ff8ce0429ad889848dc789edf56e8'/>
<id>urn:sha1:3550d6225b1ff8ce0429ad889848dc789edf56e8</id>
<content type='text'>
This reverts commit "Revert "Add DPCD writes at key points" ".
The following patch will fix the system hang issue.

v2: squash in indentation warning fix

Signed-off-by: Leo (Hanghong) Ma &lt;hanghong.ma@amd.com&gt;
Acked-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix HDMI deep color output for DCE 6-11.</title>
<updated>2021-01-25T22:49:47Z</updated>
<author>
<name>Mario Kleiner</name>
<email>mario.kleiner.de@gmail.com</email>
</author>
<published>2021-01-21T06:17:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=efa18405baa55a864c61d2f3cc6fe4d363818eb3'/>
<id>urn:sha1:efa18405baa55a864c61d2f3cc6fe4d363818eb3</id>
<content type='text'>
This fixes corrupted display output in HDMI deep color
10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3.

It will hopefully also provide fixes for other DCE's up to
DCE-11, assuming those will need similar fixes, but i could
not test that for HDMI due to lack of suitable hw, so viewer
discretion is advised.

dce110_stream_encoder_hdmi_set_stream_attribute() is used for
HDMI setup on all DCE's and is missing color_depth assignment.

dce110_program_pix_clk() is used for pixel clock setup on HDMI
for DCE 6-11, and is missing color_depth assignment.

Additionally some of the underlying Atombios specific encoder
and pixelclock setup functions are missing code which is in
the classic amdgpu kms modesetting path and the in the radeon
kms driver for DCE6/DCE8.

encoder_control_digx_v3() - Was missing setup code wrt. amdgpu
and radeon kms classic drivers. Added here, but untested due to
lack of suitable test hw.

encoder_control_digx_v4() - Added missing setup code.
Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color
output at 10 bpc and 12 bpc.

Note that encoder_control_digx_v5() has proper setup code in place
and is used, e.g., by DCE-11.2, but this code wasn't used for deep
color setup due to the missing cntl.color_depth setup in the calling
function for HDMI.

set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon
kms. Added here, but untested due to lack of hw.

set_pixel_clock_v6() - Missing setup code added. Successfully tested
on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI
deep color output with 10 bpc or 12 bpc.

Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Mario Kleiner &lt;mario.kleiner.de@gmail.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display/dc/dce/dce_stream_encoder: Remove unused variable 'regval'</title>
<updated>2021-01-11T21:09:13Z</updated>
<author>
<name>Lee Jones</name>
<email>lee.jones@linaro.org</email>
</author>
<published>2021-01-08T20:14:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c8e9b5ec9b1c2a6d20a266b5aac0775b2098c4e3'/>
<id>urn:sha1:c8e9b5ec9b1c2a6d20a266b5aac0775b2098c4e3</id>
<content type='text'>
Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c: In function ‘dce110_update_generic_info_packet’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c:70:11: warning: variable ‘regval’ set but not used [-Wunused-but-set-variable]

Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: "Christian König" &lt;christian.koenig@amd.com&gt;
Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Cc: George Shen &lt;george.shen@amd.com&gt;
Cc: Eric Bernstein &lt;eric.bernstein@amd.com&gt;
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Move common speakersToChannels definition to hw_shared.h</title>
<updated>2020-11-10T19:25:15Z</updated>
<author>
<name>Eric Bernstein</name>
<email>eric.bernstein@amd.com</email>
</author>
<published>2020-10-26T17:33:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=06d55ffaeaea9badfee7376100759f1f86397e94'/>
<id>urn:sha1:06d55ffaeaea9badfee7376100759f1f86397e94</id>
<content type='text'>
Signed-off-by: Eric Bernstein &lt;eric.bernstein@amd.com&gt;
Acked-by: Bindu Ramamurthy &lt;bindu.r@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rename set_mst_bandwidth to align with DP spec</title>
<updated>2020-09-15T21:52:41Z</updated>
<author>
<name>George Shen</name>
<email>george.shen@amd.com</email>
</author>
<published>2020-08-18T22:42:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6c95320d01dcac321e9e89903a26a840838a0ef6'/>
<id>urn:sha1:6c95320d01dcac321e9e89903a26a840838a0ef6</id>
<content type='text'>
[Why]
The function set_mst_bandwidth is poorly name since it isn't clear what
it does, and it also does not reflect any part of the allocation sequence
described in the DP spec.

[How]
Rename the function set_mst_bandwidth to set_throttled_vcp_size.

Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove set but not used variable 'speakers' in dce_stream_encoder.c</title>
<updated>2020-04-30T20:49:12Z</updated>
<author>
<name>Zheng Bin</name>
<email>zhengbin13@huawei.com</email>
</author>
<published>2020-04-30T03:40:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=83700e20b8707cb90bb64f87e24c3359aa5641da'/>
<id>urn:sha1:83700e20b8707cb90bb64f87e24c3359aa5641da</id>
<content type='text'>
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:1339:11: warning: variable ‘speakers’ set but not used [-Wunused-but-set-variable]

It is introduced by commit 4562236b3bc0 ("drm/amd/dc:
Add dc display driver (v2)"), but never used, so remove it.

Reported-by: Hulk Robot &lt;hulkci@huawei.com&gt;
Signed-off-by: Zheng Bin &lt;zhengbin13@huawei.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: rename DCN1_0 kconfig to DCN</title>
<updated>2019-11-13T20:29:44Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2019-11-06T19:48:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b86a1aa36a92bcfbc062c5e99c1d084f27f25bab'/>
<id>urn:sha1:b86a1aa36a92bcfbc062c5e99c1d084f27f25bab</id>
<content type='text'>
Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.

Change it to "dcn" to make it generic

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP</title>
<updated>2019-11-13T20:29:43Z</updated>
<author>
<name>Anthony Koo</name>
<email>Anthony.Koo@amd.com</email>
</author>
<published>2019-10-17T03:44:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5ed78cd69a1bf64e6bdb70a05c1c9bde87b209ad'/>
<id>urn:sha1:5ed78cd69a1bf64e6bdb70a05c1c9bde87b209ad</id>
<content type='text'>
[Why]
It is confusing to sinks if we send VSC SDP only on some format. Today we
signal colorimetry format using MSA while in formats like sRGB.
But when we switch to BT2020 we set the bit to ignore MSA  colorimetry and
instead use the colorimetry information in the VSC SDP.

But if sink supports signaling of colorimetry via VSC SDP we should always
set the MSA MISC1 bit 6, instead of doing so selectively.

[How]
If sink supports signaling of colorimetry via VSC SDP, and we are sending
the colorimetry info via VSC SDP with packet revision 05h, then always
set MSA MISC1 bit 6.

Signed-off-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: enabling seamless boot sequence for dcn2</title>
<updated>2019-08-15T15:54:27Z</updated>
<author>
<name>Martin Leung</name>
<email>martin.leung@amd.com</email>
</author>
<published>2019-07-17T20:08:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e'/>
<id>urn:sha1:5ec43eda85506ddc2f91c3a4e28b38da3f14cf1e</id>
<content type='text'>
[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes

[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.

This is part 2 of 2 for seamless boot NV10

Signed-off-by: Martin Leung &lt;martin.leung@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset</title>
<updated>2019-08-15T15:52:59Z</updated>
<author>
<name>Wenjing Liu</name>
<email>Wenjing.Liu@amd.com</email>
</author>
<published>2019-07-10T22:35:18Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ac42fd639550b386c41d8f3f2dc657d96fde7235'/>
<id>urn:sha1:ac42fd639550b386c41d8f3f2dc657d96fde7235</id>
<content type='text'>
[why]
hdmi data scramble and tmds rate is not reset during pipe reset.

[how]
reset hdmi tmds rate and data scramble on pipe reset

Signed-off-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Reviewed-by: Chris Park &lt;Chris.Park@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
