<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2024-07-23T21:07:11Z</updated>
<entry>
<title>drm/amd/display: Refactoring MPC</title>
<updated>2024-07-23T21:07:11Z</updated>
<author>
<name>Mounika Adhuri</name>
<email>moadhuri@amd.com</email>
</author>
<published>2024-06-26T13:21:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5ed9481db74740fd33ec4079b29db88e8c9f4a1c'/>
<id>urn:sha1:5ed9481db74740fd33ec4079b29db88e8c9f4a1c</id>
<content type='text'>
[Why]
To refactor MPC files

[How]
Moved MPC files to respective folders and
updated makefiles appropriately.

Reviewed-by: Martin Leung &lt;martin.leung@amd.com&gt;
Signed-off-by: Jerry Zuo &lt;jerry.zuo@amd.com&gt;
Signed-off-by: Mounika Adhuri &lt;moadhuri@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add misc DC changes for DCN401</title>
<updated>2024-04-26T21:23:34Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2024-03-20T17:56:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=00c391102abc13763e2bfc90e05503109b19f074'/>
<id>urn:sha1:00c391102abc13763e2bfc90e05503109b19f074</id>
<content type='text'>
Add miscellaneous changes to enable DCN401 init

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;rodrigo.siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix uninitialized variables in DC</title>
<updated>2024-04-26T21:22:44Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2024-04-16T01:05:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ba3193fa8fc8910f724b67a523ec67ee24997d3e'/>
<id>urn:sha1:ba3193fa8fc8910f724b67a523ec67ee24997d3e</id>
<content type='text'>
This fixes 49 UNINIT issues reported by Coverity.

Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove MPC rate control logic from DCN30 and above</title>
<updated>2024-03-27T13:27:09Z</updated>
<author>
<name>George Shen</name>
<email>george.shen@amd.com</email>
</author>
<published>2024-02-17T00:37:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=edfa93d87fc46913868481fe8ed3fb62c891ffb5'/>
<id>urn:sha1:edfa93d87fc46913868481fe8ed3fb62c891ffb5</id>
<content type='text'>
[Why]
MPC flow rate control is not needed for DCN30 and above. Current logic
that uses it can result in underflow for certain edge cases (such as
DSC N422 + ODM combine + 422 left edge pixel).

[How]
Remove MPC flow rate control logic and programming for DCN30 and above.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: George Shen &lt;george.shen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: create DCN3-specific log for MPC state</title>
<updated>2024-01-22T22:13:27Z</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2023-11-28T17:52:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6348469450d65270e225e1479a97c966975181b2'/>
<id>urn:sha1:6348469450d65270e225e1479a97c966975181b2</id>
<content type='text'>
Logging DCN3 MPC state was following DCN1 implementation that doesn't
consider new DCN3 MPC color blocks. Create new elements according to
DCN3 MPC color caps and a new DCN3-specific function for reading MPC
data.

v3:
- remove gamut remap reg reading in favor of fixed31_32 matrix data

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add get_gamut_remap helper for MPC3</title>
<updated>2024-01-22T22:13:26Z</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2023-11-28T17:52:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aa708057c410175879dcdcdc8bdccd9b1f06e413'/>
<id>urn:sha1:aa708057c410175879dcdcdc8bdccd9b1f06e413</id>
<content type='text'>
We want to be able to read the MPC's gamut remap matrix similar to
what we do with .dpp_get_gamut_remap functions. On the other hand, we
don't need a hook here because only DCN3+ has the MPC gamut remap
block, being absent in previous families.

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: PQ tail accuracy</title>
<updated>2023-08-30T18:58:33Z</updated>
<author>
<name>Krunoslav Kovac</name>
<email>krunoslav.kovac@amd.com</email>
</author>
<published>2023-08-08T18:33:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4d5fd3d08ea9926fb2031ff7cfb4d72b7c950301'/>
<id>urn:sha1:4d5fd3d08ea9926fb2031ff7cfb4d72b7c950301</id>
<content type='text'>
[WHY &amp; HOW]
HW LUTs changed slightly in DCN3: 256 base+slope pairs were replaced by
257 bases. Code was still calculating all 256 base+slope and then
creating 257th pt as last base + last slope.
This was done in wrong format, and then "fixed" it by making the last
two points the same thus making the last slope=0.
However, this also created some precision problems near the end that
are not visible but they do show up with capture cards.

Solution is to calculate 257 and remove deltas since we no longer have
those HW registers.

Reviewed-by: Anthony Koo &lt;anthony.koo@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Krunoslav Kovac &lt;krunoslav.kovac@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: change several dcn30 variables storage-class-specifier to static</title>
<updated>2023-03-07T19:22:42Z</updated>
<author>
<name>Tom Rix</name>
<email>trix@redhat.com</email>
</author>
<published>2023-03-05T12:52:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b79f85b7aa5a9ff9f702f40c6a5fe4a53e965cf6'/>
<id>urn:sha1:b79f85b7aa5a9ff9f702f40c6a5fe4a53e965cf6</id>
<content type='text'>
smatch reports these similar problems in dcn30
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dwb.c:223:25:
  warning: symbol 'dcn30_dwbc_funcs' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mmhubbub.c:214:28:
  warning: symbol 'dcn30_mmhubbub_funcs' was not declared. Should it be static?
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:1402:24:
  warning: symbol 'dcn30_mpc_funcs' was not declared. Should it be static?

All of these are only used in their definition file, so they should be static

Signed-off-by: Tom Rix &lt;trix@redhat.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Clean up some inconsistent indenting</title>
<updated>2022-07-28T20:05:15Z</updated>
<author>
<name>Jiapeng Chong</name>
<email>jiapeng.chong@linux.alibaba.com</email>
</author>
<published>2022-07-26T07:25:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e3b2bbb33e26d0a0327f878782632ec35cf96a72'/>
<id>urn:sha1:e3b2bbb33e26d0a0327f878782632ec35cf96a72</id>
<content type='text'>
No functional modification involved.

smatch warnings:

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:116 mpc3_get_ogam_current() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:445 mpc3_get_shaper_current() warn: inconsistent indenting.

Reported-by: Abaci Robot &lt;abaci@linux.alibaba.com&gt;
Signed-off-by: Jiapeng Chong &lt;jiapeng.chong@linux.alibaba.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add dependant changes for DCN32/321</title>
<updated>2022-06-03T20:43:38Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2022-02-23T22:48:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d3dfceb58de5f897640cdd424f6c2538d9514367'/>
<id>urn:sha1:d3dfceb58de5f897640cdd424f6c2538d9514367</id>
<content type='text'>
[Why&amp;How]
This patch adds necessary changes needed in DC files outside DCN32/321
specific tree

v2: squash in updates (Alex)

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
