linux/drivers/gpu/drm/amd/display/dc/dml/dcn321, branch master

drm/amd/display: Array offset used before range check

2025-08-27T17:57:50Z

Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/offset-use-before-range-check Reviewed-by: Joshua Aberback Signed-off-by: Clay King Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove old comments

2024-07-23T21:38:29Z

Remove some old comments from DCN32/321. Signed-off-by: Rodrigo Siqueira Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: Fix index may exceed array range within fpu_update_bw_bounding_box

2024-05-02T20:18:18Z

[Why] Coverity reports OVERRUN warning. soc.num_states could be 40. But array range of bw_params->clk_table.entries is 8. [How] Assert if soc.num_states greater than 8. Reviewed-by: Alex Hung Acked-by: Tom Chung Signed-off-by: Hersen Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Introduce DML2

2023-10-09T20:48:51Z

DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Co-developed-by: Roman Li Signed-off-by: Roman Li Signed-off-by: Qingqing Zhuo Signed-off-by: Alex Deucher

drm/amd/display: Disable DC Mode Capping On DCN321

2023-06-23T19:43:32Z

Why: Limiting clocks to DC mode max results in some display modes to no longer be supported How: Disable the path that limits the clock values Fixes: 3b718dcaf163 ("drm/amd/display: Filter out AC mode frequencies on DC mode systems") Reviewed-by: Martin Leung Acked-by: Hamza Mahfooz Signed-off-by: Austin Zheng Signed-off-by: Alex Deucher

drm/amd/display: Add Clock Table Entry With Max DC Values

2023-06-23T19:40:50Z

Why: Certain display configs resulted in underflow How: Add an entry containing all max DC clock timings Reviewed-by: Alvin Lee Acked-by: Hamza Mahfooz Signed-off-by: Austin Zheng Signed-off-by: Alex Deucher

drm/amd/display: Filter out AC mode frequencies on DC mode systems

2023-06-09T16:50:55Z

Why: Limit maximum clock speeds to DC mode limits for DC mode systems How: Store DC mode limits when individual clocks are initialized and cap the values when building the clock table Acked-by: Stylon Wang Signed-off-by: Austin Zheng Reviewed-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: clean up some inconsistent indenting

2023-06-09T15:08:29Z

No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.c:556 dcn321_update_bw_bounding_box_fpu() warn: inconsistent indenting. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5304 Signed-off-by: Jiapeng Chong Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd/display: Clean FPGA code in dc

2023-06-09T14:44:11Z

[Why] Drop dead code for Linux. [How] Remove all IS_FPGA_MAXIMUS_DC and IS_DIAG_DC Reviewed-by: Ariel Bernstein Acked-by: Tom Chung Signed-off-by: Qingqing Zhuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Update bounding box values for DCN321

2023-04-21T12:49:37Z

[Why&how] Update bounding box values as per hardware spec Fixes: 197485c69543 ("drm/amd/display: Create dcn321_fpu file") Acked-by: Leo Li Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher