linux/drivers/gpu/drm/amd/display/dc/dml2, branch master

drm/amd/display: Rename dml2 to dml2_0 folder

2025-10-28T13:57:39Z

[Why] dml2 folder contains all logic for all versions of DML2 This is currently DML2.0 and DML2.1. Rename dml2 to dml2_0 folder to reflect this better (dml2_0 for DML2.0). [How] Rename dml2 to dml2_0 folder and update dml2 references to use dml2_0 folder. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: waynelin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add opp count validation to dml2.1

2025-10-28T13:57:27Z

Newer asics can have mismatching dpp and opp counts and dml needs to account for this. Reviewed-by: Charlene Liu Signed-off-by: Dmytro Laktyushkin Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Bump minimum for frame_warn_limit

2025-10-28T13:56:56Z

[Why] The bigger of CONFIG_FRAME_WARN and frame_warn_limit is used to trigger warnings about large stack frames. The dml_core_mode_support() stack frame has grown to 2056. [How] Update frame_warn_limit to 2056 so that CONFIG_FRAME_WARN of 2048 doesn't cause a failure. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4609 Reviewed-by: Aurabindo Pillai Signed-off-by: Mario Limonciello Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix typo in display_mode_core_structs.h

2025-10-20T22:20:40Z

Fix a typo in a comment, change "enviroment" to "environment" in drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h Signed-off-by: Aditya Gollamudi Signed-off-by: Alex Deucher

drm/amd/display: Remove unused field in DML

2025-10-20T22:20:31Z

Remove unused fields. Reviewed-by: Austin Zheng Signed-off-by: Alvin Lee Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: Consolidate two DML2 FP guards

2025-10-13T18:14:31Z

[Why&How] Consolidate two FP guards into one in dml2 since they are separated by one line of code, independent from the guard. Reviewed-by: Dillon Varone Signed-off-by: Ivan Lipski Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: DML2.1 Reintegration

2025-10-13T18:14:31Z

[Summary of changes] - Updated structs - Renaming of variables for clarity Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Optimize remove_duplicates() from O(N^2) to O(N)

2025-09-23T14:36:53Z

Replace the previous O(N^2) implementation of remove_duplicates() with a O(N) version using a fast/slow pointer approach. The new version keeps only the first occurrence of each element and compacts the array in place, improving efficiency without changing functionality. Signed-off-by: Kuan-Wei Chiu Reviewed-by: Alex Hung Signed-off-by: Alex Deucher

drm/amd/display/dml2: Guard dml21_map_dc_state_into_dml_display_cfg with DC_FP_START

2025-09-15T21:04:06Z

dml21_map_dc_state_into_dml_display_cfg calls (the call is usually inlined by the compiler) populate_dml21_surface_config_from_plane_state and populate_dml21_plane_config_from_plane_state which may use FPU. In a x86-64 build: $ objdump --disassemble=dml21_map_dc_state_into_dml_display_cfg \ > drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.o | > grep %xmm -c 63 Thus it needs to be guarded with DC_FP_START. But we must note that the current code quality of the in-kernel FPU use in AMD dml2 is very much problematic: we are actually calling DC_FP_START in dml21_wrapper.c here, and this translation unit is built with CC_FLAGS_FPU. Strictly speaking this does not make any sense: with CC_FLAGS_FPU the compiler is allowed to generate FPU uses anywhere in the translated code, perhaps out of the DC_FP_START guard. This problematic pattern also occurs in at least dml2_wrapper.c, dcn35_fpu.c, and dcn351_fpu.c. Thus we really need a careful audit and refactor for the in-kernel FPU uses, and this patch is simply whacking a mole. However per the reporter, whacking this mole is enough to make a 9060XT "just work." Reported-by: Asiacn <710187964@qq.com> Closes: https://github.com/loongson-community/discussions/issues/102 Tested-by: Asiacn <710187964@qq.com> Signed-off-by: Xi Ruoyao Reviewed-by: Huacai Chen Reviewed-by: Alex Hung Signed-off-by: Alex Deucher

drm/amd/display: Add DSC padding for OVT Support

2025-09-15T21:01:11Z

[Why] -Certain OVT timings require DSC configurations which divide the horizontal active unevenly across DSC slices -DSC slices must be even, so padding needs to be added to the active to make this possible -The pixel clock of the HW now needs to be increased to accommodate the extra padded pixels -To keep the line time the same, the blank of the HW timing needs to be increased as well [How] -Calculate h_active padding, h_total padding, and pixel clock based off of the original OVT timing and DSC calculations -Store these values in the pipe and program HW with these modifications -Added general support for cases where DSC slice config does not evenly split the horizontal active by fixing some slice width calculations -Updated PPS calculations for these cases Reviewed-by: Chris Park Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher