linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src, branch master

drm/amd/display: Fix bounds checking in dml2_0 clock table array

2026-03-30T18:40:20Z

[Why] Multiple locations in dml2_0 used num_clk_values-1 as array index without checking if num_clk_values > 0. When num_clk_values is 0, this results in accessing array index -1, which wraps to 255 for unsigned types, causing out-of-bounds memory access and potential crashes. [How] Add proper bounds checking using ternary operators to guard all num_clk_values-1 array accesses. When num_clk_values is 0, return 0 as fallback value instead of accessing invalid memory. This prevents buffer overflows while maintaining backward compatibility and provides sensible default behavior for empty clock tables. Reviewed-by: Dillon Varone Signed-off-by: Gabe Teeger Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher

drm/amd/display: clean up typecasts and constants in dcn4_calcs

2026-03-24T17:33:09Z

Signed-off-by: Adriano Vero Signed-off-by: Alex Deucher

drm/amd/display: Plumb MRQ programming out of DML for dml2_1

2026-03-17T14:35:54Z

[Why] If the MRQ is present then these fields are also required to be plumbed out to the requestor for programming. [How] Pipe the fields out through rq_dlg_get_rq_reg. The implementation follows the previous generation in dml2_0 for DCN35 but adjusted for the new helpers and coding style of dml2_1. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix number of opp

2026-03-17T14:35:47Z

[Why/How] Patch number of opp based on IP caps Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Chuanyu Tseng Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Sync dcn42 with DC 3.2.373

2026-03-11T17:58:07Z

This patch provides a bulk merge to align driver support for DCN42 with Display Core version 3.2.373. It includes upgrade for: - clk_mgr - dml2/dml21 - optc - hubp - mpc - optc - hwseq Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add DML support for dcn42

2026-03-11T17:58:06Z

DML support for DCN 4.2 Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Match expected data types

2026-02-03T21:43:08Z

[Why/How] Data types should match what is expected. Update/cast data accordingly. Also change ASSERT to use DML_ASSERT instead Reviewed-by: Dillon Varone Signed-off-by: Zheng Austin Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add lpddr5 handling to dml2.1

2026-02-03T21:39:15Z

[Why & How] Memory bandwidth calculations work differently than for ddr. Add lpddr5 handling. Reviewed-by: Charlene Liu Signed-off-by: Dmytro Laktyushkin Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix presentation of Z8 efficiency

2025-12-16T18:25:22Z

[Why/How] Should differentiate when vblank is or isn't included Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Chenyu Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add use_max_lsw parameter

2025-12-16T18:25:17Z

[WHY&HOW] Add use_max_lsw parameter to make prefetch for linear surfaces similar to tiled. Reviewed-by: Dillon Varone Signed-off-by: Oleh Kuzhylnyi Signed-off-by: Chenyu Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher