linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35, branch master

drm/amd/display: Add more DC HW state info to underflow logging

2025-10-28T13:57:44Z

[Why] Debugging underflow issues frequently requires knowing the HW state at the time of underflow. To enable capturing this HW state information, interface functions are needed for the various DC HW blocks. [How] This change adds the interface functions to read HW state for the following DC HW blocks: - HUBBUB - HUBP - DPP - MPC - OPP - DSC - OPTC - DCCG Reviewed-by: George Shen Signed-off-by: Karen Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Update IPS sequential_ono requirement checks

2025-05-05T16:54:12Z

[why & how] ASICs that require special RCG/PG programming are determined based on hw_internal_rev. Update these checks to properly include all such ASICs. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35

2024-10-22T21:50:38Z

[WHY & HOW] Cursor corruption observed on USBC display with specific system setup with a reboot. Cursor memory might still in the lightsleep state due to voltage issue, we need program DISPCLK_R_GATE_DISABLE to avoid this issue only on DCN35. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Yihan Zhu Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: correct register Clock Gater incorrectly disabled

2024-10-01T21:32:29Z

[why] The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater when the DPP is enabled. The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode. This will disable the clock gater and the DPPCLK register clock branch will always be running. As a consequence, the dynamic power will be higher than expected. Reviewed-by: Alvin Lee Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Implement bias and scale pre scl

2024-07-23T21:07:10Z

why: New scaler needs the input to be full range color space. This will also fix issues that come up due to not having a predefined limited color space matrix for certain color spaces how: Use bias and scale HW to expand the range of limited color spaces to full before the scaler Reviewed-by: Krunoslav Kovac Signed-off-by: Jerry Zuo Signed-off-by: Relja Vojvodic Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove unnecessary files

2024-04-30T13:52:21Z

[Why & How] We accidentally upstream unnecessary files. Remove them. Reviewed-by: Tom Chung Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Toggle additional RCO options in DCN35

2024-04-10T01:59:07Z

[Why] With root clock optimization now enabled for DCN35 there are still RCO registers still not being toggled [How] Add in logic to toggle RCO registers for DPPCLK, DPSTREAMCLK and DSCCLK Reviewed-by: Charlene Liu Acked-by: Roman Li Signed-off-by: Daniel Miess Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Refactor DPP into a component directory

2024-03-20T17:37:37Z

[WHY & HOW] Move all dpp files to a new dpp directory. Reviewed-by: Martin Leung Acked-by: Alex Hung Signed-off-by: Revalla Hari Krishna Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher