linux/drivers/gpu/drm/amd/display/dc/dsc, branch master

drm/amd/display: Make DSC FGCG a DSC block level function

2026-02-03T21:39:37Z

[Why] FGCG shouldn't be called at the DC resource level as part of DSC creation because dc_create is intended for SW init, not HW init, and register access is not guaranteed to work at this phase. [How] Add a set_fgcg function at the DSC interface level. Existing ASIC can continue using the function in DC resource to retain current compatibility but further development should favor calling the function pointer during init_hw (if it exists). Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: fix misspelling of "minimum" in dc_dsc.c

2026-01-20T22:25:59Z

Fix the typo "miniumum" → "minimum" in a comment in dc_dsc.c. This typo is already listed in scripts/spelling.txt by commit 8c3200265787 ("scripts/spelling.txt: add several more common spelling mistakes"). Suggested-by: Cryolitia PukNgae Signed-off-by: Runrun Liu Signed-off-by: Alex Deucher

drm/amd/display: refactor DSC cap calculation for dcn35

2025-11-12T02:54:15Z

why: dcn35 currently uses a hardcoded DSC display clock value which is incorrect for some asic types. Newer DCN versions retrieve dsc display clock from clk_mgr. The same can be done for dcn35. how: Refactor the DSC cap calculation using pre-existing logic. Handle ODM combine requirements in dc_dsc.c. Replace hardcoded display clock with actual value retrieved from clk_mgr. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Charlene Liu Reviewed-by: Wenjing Liu Signed-off-by: Mohit Bawa Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add more DC HW state info to underflow logging

2025-10-28T13:57:44Z

[Why] Debugging underflow issues frequently requires knowing the HW state at the time of underflow. To enable capturing this HW state information, interface functions are needed for the various DC HW blocks. [How] This change adds the interface functions to read HW state for the following DC HW blocks: - HUBBUB - HUBP - DPP - MPC - OPP - DSC - OPTC - DCCG Reviewed-by: George Shen Signed-off-by: Karen Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Correct slice width calculation for YCbCr420

2025-10-13T18:14:31Z

[Why] -OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to incorrect slice width being calculated [How] -Ensure slice width is divisible by 2 for 420 to comply with spec Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add DSC padding for OVT Support

2025-09-15T21:01:11Z

[Why] -Certain OVT timings require DSC configurations which divide the horizontal active unevenly across DSC slices -DSC slices must be even, so padding needs to be added to the active to make this possible -The pixel clock of the HW now needs to be increased to accommodate the extra padded pixels -To keep the line time the same, the blank of the HW timing needs to be increased as well [How] -Calculate h_active padding, h_total padding, and pixel clock based off of the original OVT timing and DSC calculations -Store these values in the pipe and program HW with these modifications -Added general support for cases where DSC slice config does not evenly split the horizontal active by fixing some slice width calculations -Updated PPS calculations for these cases Reviewed-by: Chris Park Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Consider sink max slice width limitation for dsc

2025-08-27T17:57:50Z

[WHY&HOW] The sink max slice width limitation should be considered for DSC, but was removed in "refactor DSC cap calculations". This patch adds it back and takes the valid minimum between the sink and source. Signed-off-by: Dillon Varone Signed-off-by: Aurabindo Pillai Reviewed-by: Wenjing Liu Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix divide by zero when calculating min ODM factor

2025-07-28T20:24:05Z

[WHY&HOW] If the debug option is set to disable_dsc the max slice width and/or dispclk can be zero. This causes a divide by zero when calculating the min ODM combine factor. Add a check to ensure they are valid first. Reviewed-by: Wenjing Liu Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd/display: Refactor DSC cap calculations

2025-07-15T18:07:51Z

[WHY] DSC block level should only be responsible for reporting single DSC instance capabilities. Factoring in ODM combine requirements should be handled in dc_dsc.c. Both components should acquire clocks from clk_mgr to determine throughput capabilities instead of relying on hard coded values as these can differ by SoC and SKU. [HOW] 1) Add dsc_get_single_enc_caps to acquire single DSC instance capabilities (replacing dsc_get_enc_caps), factoring in DSCCLK 2) add build_dsc_enc_caps to combine single DSC instance capabilities 3) account for max pixel rate per pipe (DISPCLK) when calculating minimum slice count Reviewed-by: Wenjing Liu Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Make dcn401_initialize_min_clocks() available to other compilation units

2025-07-15T18:07:51Z

[Why & How] Expose dcn401_initialize_min_clocks() for future use and add additional check for IP register. Reviewed-by: Nevenko Stupar Signed-off-by: Karthi Kandasamy Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher