<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/dc/hubp, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2026-03-30T19:12:15Z</updated>
<entry>
<title>drm/amd/display: Fixed Silence complier warnings in dc</title>
<updated>2026-03-30T19:12:15Z</updated>
<author>
<name>Gaghik Khachatrian</name>
<email>gaghik.khachatrian@amd.com</email>
</author>
<published>2026-03-09T21:18:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f82480fafedf622541276d48a3b4fed20ce5d866'/>
<id>urn:sha1:f82480fafedf622541276d48a3b4fed20ce5d866</id>
<content type='text'>
[Why]
Resolve compiler warnings by marking unused parameters explicitly.

[How]
In .c and .h function definitions, keep parameter names
in signatures and add a line with `(void)param;` in function body

Preserved function signatures and avoids breaking code paths that
may reference the parameter under conditional compilation.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Reviewed-by: Austin Zheng &lt;austin.zheng@amd.com&gt;
Signed-off-by: Gaghik Khachatrian &lt;gaghik.khachatrian@amd.com&gt;
Signed-off-by: Chuanyu Tseng &lt;chuanyu.tseng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add MRQ programming for DCN42</title>
<updated>2026-03-23T18:11:13Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2026-03-02T20:02:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=24ccc041f0a8100cc7aae822a3328b276039fe59'/>
<id>urn:sha1:24ccc041f0a8100cc7aae822a3328b276039fe59</id>
<content type='text'>
[Why]
DCN401 didn't have a MRQ present so these fields didn't exist.

They are still present on DCN42 so we need to continue programming
them like we did on DCN35 or we can block have poor meta requesting
efficiency which blocks p-state.

[How]
Add `hubp42_program_requestor` which takes DML21 input and programs
the registers like DCN35 and prior.

Reviewed-by: Leo Chen &lt;leo.chen@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Chuanyu Tseng &lt;Chuanyu.Tseng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Clamp dc_cursor_position x_hotspot to prevent integer overflow</title>
<updated>2026-03-17T14:36:09Z</updated>
<author>
<name>Benjamin Nwankwo</name>
<email>Benjamin.Nwankwo@amd.com</email>
</author>
<published>2026-03-06T17:49:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a2aa7987de1169548c465f6cc1019d2112e0e8b5'/>
<id>urn:sha1:a2aa7987de1169548c465f6cc1019d2112e0e8b5</id>
<content type='text'>
why:
Workaround for duplicate cursor. Cursor offsetting via x_hotspot attempts
to write a 32 bit unsigned integer to the 8 bit field CURSOR_HOT_SPOT_X.
This wraps cursor position back into focus if x_hotspot exceeds 8 bits,
making duplicate cursors visible

how:
Clamp x_hotspot before writing to hardware

Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Reviewed-by: Nevenko Stupar &lt;nevenko.stupar@amd.com&gt;
Signed-off-by: Benjamin Nwankwo &lt;Benjamin.Nwankwo@amd.com&gt;
Signed-off-by: Chuanyu Tseng &lt;chuanyu.tseng@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Sync dcn42 with DC 3.2.373</title>
<updated>2026-03-11T17:58:07Z</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2026-03-05T17:56:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e56e3cff2a1bb29545ddbec562e76c0419363a40'/>
<id>urn:sha1:e56e3cff2a1bb29545ddbec562e76c0419363a40</id>
<content type='text'>
This patch provides a bulk merge to align driver
support for DCN42 with Display Core version 3.2.373.

It includes upgrade for:
- clk_mgr
- dml2/dml21
- optc
- hubp
- mpc
- optc
- hwseq

Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable dcn42 DC</title>
<updated>2026-02-23T19:28:33Z</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2026-02-02T23:47:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6b2dd7d37badd8bf076875397f9f39b494258ca7'/>
<id>urn:sha1:6b2dd7d37badd8bf076875397f9f39b494258ca7</id>
<content type='text'>
Add support for DCN 4.2 in Display Core

Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add dcn42 DC resources</title>
<updated>2026-02-23T19:28:33Z</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2026-02-02T23:06:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bd096a56da7cad1c93c0138a64478b43f5a94736'/>
<id>urn:sha1:bd096a56da7cad1c93c0138a64478b43f5a94736</id>
<content type='text'>
Display Core resources for DCN 4.2:
- CLK_MGR
- DCCG
- DIO
- DPP
- GPIO
- HPO
- HUBBUB
- HUBP
- HWSS
- IRQ
- MMHUBBUB
- MPC
- OPTC
- PG

Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix wrong x_pos and y_pos for cursor offload</title>
<updated>2025-12-08T18:56:40Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2025-11-12T15:58:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c02288724b98cbc018231200891d66578f83f848'/>
<id>urn:sha1:c02288724b98cbc018231200891d66578f83f848</id>
<content type='text'>
[Why]
The hubp401_cursor_set_position function programs a different value
than it stores for use with cursor offload.

This can cause a desync when switching between cursor programming paths.

[How]
We do the translation to destination space currently twice: once in the
HWSS layer, and then again in the HUBP layer since we never store the
translated result.

HUBP expects to program the pos-&gt;x and pos-&gt;y directly for other ASIC,
so follow that pattern here as well.

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update cursor offload assignments</title>
<updated>2025-10-28T13:58:18Z</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2025-10-02T16:44:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=518a368c57a0e63f531e471baa9499c45ab87f7c'/>
<id>urn:sha1:518a368c57a0e63f531e471baa9499c45ab87f7c</id>
<content type='text'>
[Why &amp; How]
- Cursor lines per chunk must be assigned from hubp-&gt;att and not
  hubp-&gt;pos (the one in hubp-&gt;pos is unassigned)
- In DCN401 DPP, cur0_enable in attribute struct must be assigned
  as this is the field passed to DMU
- DCN401 should not program position in driver if offload is enabled

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add more DC HW state info to underflow logging</title>
<updated>2025-10-28T13:57:44Z</updated>
<author>
<name>Karen Chen</name>
<email>Karen.Chen@amd.com</email>
</author>
<published>2025-10-15T15:13:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dbf58a9dad4d80286c5c17e199f595eb0dd3be5a'/>
<id>urn:sha1:dbf58a9dad4d80286c5c17e199f595eb0dd3be5a</id>
<content type='text'>
[Why]
Debugging underflow issues frequently requires knowing the
HW state at the time of underflow. To enable capturing this
HW state information, interface functions are needed for the
various DC HW blocks.

[How]
This change adds the interface functions to read HW state for
the following DC HW blocks:
- HUBBUB
- HUBP
- DPP
- MPC
- OPP
- DSC
- OPTC
- DCCG

Reviewed-by: George Shen &lt;george.shen@amd.com&gt;
Signed-off-by: Karen Chen &lt;Karen.Chen@amd.com&gt;
Signed-off-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Rename dml2 to dml2_0 folder</title>
<updated>2025-10-28T13:57:39Z</updated>
<author>
<name>Austin Zheng</name>
<email>Austin.Zheng@amd.com</email>
</author>
<published>2025-10-21T05:52:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e6a8a000cfe6a1106c17ab4a47eb6dd21596968c'/>
<id>urn:sha1:e6a8a000cfe6a1106c17ab4a47eb6dd21596968c</id>
<content type='text'>
[Why]
dml2 folder contains all logic for all versions of DML2
This is currently DML2.0 and DML2.1.
Rename dml2 to dml2_0 folder to reflect this better (dml2_0
for DML2.0).

[How]
Rename dml2 to dml2_0 folder and update dml2 references to
use dml2_0 folder.

Reviewed-by: Dillon Varone &lt;dillon.varone@amd.com&gt;
Signed-off-by: Austin Zheng &lt;Austin.Zheng@amd.com&gt;
Signed-off-by: waynelin &lt;Wayne.Lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
