linux/drivers/gpu/drm/amd/display/dc/optc/dcn32, branch master

drm/amd/display: Fixed Silence complier warnings in dc

2026-03-30T19:12:15Z

[Why] Resolve compiler warnings by marking unused parameters explicitly. [How] In .c and .h function definitions, keep parameter names in signatures and add a line with `(void)param;` in function body Preserved function signatures and avoids breaking code paths that may reference the parameter under conditional compilation. Reviewed-by: Dillon Varone Reviewed-by: Austin Zheng Signed-off-by: Gaghik Khachatrian Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher

drm/amd/display: Add more DC HW state info to underflow logging

2025-10-28T13:57:44Z

[Why] Debugging underflow issues frequently requires knowing the HW state at the time of underflow. To enable capturing this HW state information, interface functions are needed for the various DC HW blocks. [How] This change adds the interface functions to read HW state for the following DC HW blocks: - HUBBUB - HUBP - DPP - MPC - OPP - DSC - OPTC - DCCG Reviewed-by: George Shen Signed-off-by: Karen Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: wait for otg update pending latch before clock optimization

2025-08-27T17:57:50Z

[WHY & HOW] OTG pending update unlatched will cause system fail, wait OTG fully disabled to avoid this error. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Yihan Zhu Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Constify struct timing_generator_funcs

2025-05-29T14:57:31Z

'struct timing_generator_funcs' are not modified in these drivers. Constifying these structures moves some data to a read-only section, so increases overall security, especially when the structure holds some function pointers. Signed-off-by: Christophe JAILLET Reviewed-by: Alex Hung Signed-off-by: Alex Deucher

drm/amd/display: log destination of vertical interrupt

2025-02-13T02:02:57Z

[Why] Knowing the destination of OTG's vertical interrupt 2 is useful for debugging, but it is not currently included in the OTG state readback logic [How] Read the OTG interrupt destination register to get the vertical interrupt 2 destination on ASICs that have this register when reading back the OTG state from hardware Reviewed-by: Sung Lee Reviewed-by: Aric Cyr Signed-off-by: Josip Pavic Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Wait for all pending cleared before full update

2024-10-01T21:30:47Z

[Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates. Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Wait for double buffer update on ODM changes

2024-06-27T21:10:37Z

[WHAT & HOW] We must wait for ODM double buffer updates to complete before exiting the pipe update sequence or we may reduce DISPCLK and hit some transient underflow (pixel rate is reduced before the pipes have ODM enabled). Reviewed-by: Samson Tam Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Alex Hung Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split

2024-05-13T19:46:55Z

[WHY] Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM pipesplit is used, pixels on the left edge of ODM slices need one extra pixel from the right edge of the previous slice to calculate the correct chroma value. Without this change, the chroma value is slightly different than expected. This is usually imperceptible visually, but it impacts test pattern CRCs for compliance test automation. [HOW] Update logic to use the register for adding extra left edge pixel for YCbCr422/420 ODM cases. Reviewed-by: George Shen Acked-by: Alex Hung Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: use even ODM slice width for two pixels per container

2024-04-30T13:57:04Z

[why] When optc uses two pixel per container, each ODM slice width must be an even number. [how] If ODM slice width is odd number increase it by 1. Reviewed-by: Dillon Varone Acked-by: Wayne Lin Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

Revert "drm/amd/display: Add fallback configuration when set DRR"

2024-04-26T21:22:38Z

This reverts commit d76c0a23b557c6ebb3fac32548100d76a1e0ce23. This change must be reverted since it caused soft hangs when changing the refresh rate to 122 & 144Hz when using a 7000 series GPU. Acked-by: Alex Deucher Reviewed-by: Harry Wentland Reported-by: Mark Broadworth Cc: Daniel Wheeler Cc: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher