<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/include, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2026-03-11T14:56:00Z</updated>
<entry>
<title>drm/amd/display: Add ESD detection for replay recovery</title>
<updated>2026-03-11T14:56:00Z</updated>
<author>
<name>Weiguang Li</name>
<email>wei-guang.li@amd.com</email>
</author>
<published>2025-12-08T06:13:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=61436301dfc1d845f2b90a5f07d5c1d7cf89e900'/>
<id>urn:sha1:61436301dfc1d845f2b90a5f07d5c1d7cf89e900</id>
<content type='text'>
[HOW]
Add Replay recovery flow so that when HPD occurs and ESD is detected,
Replay can restore the system back to normal.

Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Weiguang Li &lt;wei-guang.li@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Implement BIOS parser external encoder control</title>
<updated>2026-02-23T19:28:32Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2026-01-26T21:08:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ee5c4855f43c1af96c3f7e4412ce9492b00023fe'/>
<id>urn:sha1:ee5c4855f43c1af96c3f7e4412ce9492b00023fe</id>
<content type='text'>
The VBIOS has a function called ExternalEncoderControl which
controls the DP bridge encoders that some GPUs use for analog
and LVDS output. Fixup this old functionality.

For reference, see the legacy non-DC amdgpu display code:
amdgpu_atombios_encoder_setup_external_encoder()

- Set same parameters for the ENABLE action as the SETUP action
- Add missing enum values for DDC setup and DAC load detection
- Fix the bits per color field
- Clarify the code that sets the link rate
- Expose the function so that it can be called by rest of DC

A subsequent commit will call this function from DCE HWSS.

Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add dcn42 version identifiers</title>
<updated>2026-02-23T19:16:31Z</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2026-02-02T23:18:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=619cf5be962f868f9225225e028edd1370296c90'/>
<id>urn:sha1:619cf5be962f868f9225225e028edd1370296c90</id>
<content type='text'>
Add DCN 4.2 asic version identifiers.

Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add FR skipping CTS functions</title>
<updated>2026-01-27T23:10:33Z</updated>
<author>
<name>Jack Chang</name>
<email>jack.chang@amd.com</email>
</author>
<published>2025-08-01T03:54:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7cdb3d0367860d8e5a058b8658cf7ae85a4796d3'/>
<id>urn:sha1:7cdb3d0367860d8e5a058b8658cf7ae85a4796d3</id>
<content type='text'>
1. To check whether Sink reaches maximum skipping number

Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Signed-off-by: Jack Chang &lt;jack.chang@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: PR error HPD_IRQ handling</title>
<updated>2026-01-10T19:21:53Z</updated>
<author>
<name>Jack Chang</name>
<email>jack.chang@amd.com</email>
</author>
<published>2025-11-06T02:58:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=53edf8604a7c594d1d5091deb7c11d2c3b2e6b79'/>
<id>urn:sha1:53edf8604a7c594d1d5091deb7c11d2c3b2e6b79</id>
<content type='text'>
[Why &amp; How]
Add error handling for IRQ_HPD in Panel Replay

Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Jack Chang &lt;jack.chang@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;matthew.stewart2@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DPCD for Selective Update</title>
<updated>2026-01-10T19:21:53Z</updated>
<author>
<name>Jack Chang</name>
<email>jack.chang@amd.com</email>
</author>
<published>2025-12-04T08:57:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a230696d4e009abb22b7a2f9d434f1555bfa08ca'/>
<id>urn:sha1:a230696d4e009abb22b7a2f9d434f1555bfa08ca</id>
<content type='text'>
[Why&amp;How]
Add flow to read selective update related info from DPCD,
and pass the info to DMUB.

Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Jack Chang &lt;jack.chang@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;matthew.stewart2@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Correct color depth for SelectCRTC_Source</title>
<updated>2026-01-05T22:00:00Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-12-06T02:31:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cdf6e4c0cdab129ffc4e41a8ac53a0738f805072'/>
<id>urn:sha1:cdf6e4c0cdab129ffc4e41a8ac53a0738f805072</id>
<content type='text'>
Pass the correct enum values as expected by the VBIOS.
Previously the actual bit depth integer value was passed,
which was a mistake.

Fixes: 7fb4f254c8eb ("drm/amd/display: Add SelectCRTC_Source to BIOS parser")
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Support DRR granularity</title>
<updated>2025-12-16T18:25:41Z</updated>
<author>
<name>Weiguang Li</name>
<email>wei-guang.li@amd.com</email>
</author>
<published>2025-11-27T09:49:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2f912935168a3122371f1de85eed8d9cce192d0c'/>
<id>urn:sha1:2f912935168a3122371f1de85eed8d9cce192d0c</id>
<content type='text'>
[Why&amp;How]
Support DRR granularity for coasting Vtotal calculation

Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Weiguang Li &lt;wei-guang.li@amd.com&gt;
Signed-off-by: Chenyu Chen &lt;chen-yu.chen@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: shrink struct members</title>
<updated>2025-12-08T19:25:12Z</updated>
<author>
<name>Rosen Penev</name>
<email>rosenp@gmail.com</email>
</author>
<published>2025-11-08T17:40:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3849efdc7888d537f09c3dcfaea4b3cd377a102e'/>
<id>urn:sha1:3849efdc7888d537f09c3dcfaea4b3cd377a102e</id>
<content type='text'>
On a 32-bit ARM system, the audio_decoder struct ends up being too large
for dp_retrain_link_dp_test.

link_dp_cts.c:157:1: error: the frame size of 1328 bytes is larger than
1280 bytes [-Werror=frame-larger-than=]

This is mitigated by shrinking the members of the struct and avoids
having to deal with dynamic allocation.

feed_back_divider is assigned but otherwise unused. Remove both.

pixel_repetition looks like it should be a bool since it's only ever
assigned to 1. But there are checks for 2 and 4. Reduce to uint8_t.

Remove ss_percentage_divider. Unused.

Shrink refresh_rate as it gets assigned to at most a 3 digit integer
value.

Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add panel replay enablement option and logic</title>
<updated>2025-11-18T15:50:06Z</updated>
<author>
<name>Jack Chang</name>
<email>jack.chang@amd.com</email>
</author>
<published>2025-08-21T05:19:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2e6c79e4732437f4a8e8ed37ebcb2bf843734cb2'/>
<id>urn:sha1:2e6c79e4732437f4a8e8ed37ebcb2bf843734cb2</id>
<content type='text'>
[Why&amp;How]
1.Add flow to enable and configure panel replay enablement and
configuration
2.Add registry key for enable option
3.Add replay version check to be compatible with freesync replay
4.Add AC/DC switch function to notify ac/dc change.
5.Add flow in set event function to check and decide Replay
enable/disable

Reviewed-by: Robin Chen &lt;robin.chen@amd.com&gt;
Signed-off-by: Jack Chang &lt;jack.chang@amd.com&gt;
Signed-off-by: Leon Huang &lt;Leon.Huang1@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
