<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/include, branch v5.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-10-20T19:27:31Z</updated>
<entry>
<title>drm/amdgpu: support B0&amp;B1 external revision id for yellow carp</title>
<updated>2021-10-20T19:27:31Z</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2021-10-19T03:13:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67'/>
<id>urn:sha1:53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67</id>
<content type='text'>
B0 internal rev_id is 0x01, B1 internal rev_id is 0x02.
The external rev_id for B0 and B1 is 0x20.
The original expression is not suitable for B1.

v2: squash in fix for display code (Alex)

Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: USB4 bring up set correct address</title>
<updated>2021-10-05T14:32:06Z</updated>
<author>
<name>Jude Shih</name>
<email>shenshih@amd.com</email>
</author>
<published>2021-10-04T14:40:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7ab0965079bbc0e39fe0e1df4dcdf931c9d25372'/>
<id>urn:sha1:7ab0965079bbc0e39fe0e1df4dcdf931c9d25372</id>
<content type='text'>
[Why]
YELLOW_CARP_B0 address was not correct

[How]
Set YELLOW_CARP_B0 to 0x1A.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Acked-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Signed-off-by: Jude Shih &lt;shenshih@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN</title>
<updated>2021-06-22T20:51:45Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-06-21T20:51:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8fe44c080a53ac0ccbe88053a2e40f9acca33091'/>
<id>urn:sha1:8fe44c080a53ac0ccbe88053a2e40f9acca33091</id>
<content type='text'>
No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN3.1 yellow carp asic family IDs</title>
<updated>2021-06-04T20:03:26Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-05-19T14:36:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d997ea5c58bb1c05df9e1f6eb030f6647d938eac'/>
<id>urn:sha1:d997ea5c58bb1c05df9e1f6eb030f6647d938eac</id>
<content type='text'>
[Why &amp; How]
To determine whether the chip is yellow carp or not and which revision
it is.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display/dc/gpio/gpio_service: Pass around correct dce_{version, environment} types</title>
<updated>2021-05-27T16:33:51Z</updated>
<author>
<name>Lee Jones</name>
<email>lee.jones@linaro.org</email>
</author>
<published>2021-05-26T08:47:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=353f7f3a9dd5fd2833b6462bac89ec1654c9c3aa'/>
<id>urn:sha1:353f7f3a9dd5fd2833b6462bac89ec1654c9c3aa</id>
<content type='text'>
Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c: In function ‘dal_gpio_service_create’:
 drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:71:4: warning: implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’ [-Wenum-conversion]
 drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.c:77:4: warning: implicit conversion from ‘enum dce_version’ to ‘enum dce_environment’ [-Wenum-conversion]

Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: "Christian König" &lt;christian.koenig@amd.com&gt;
Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones &lt;lee.jones@linaro.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add exit training mode and update channel coding in LT</title>
<updated>2021-05-27T16:25:43Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2021-05-03T23:35:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3df212576e8b6fb94f8e4b856d39853557d22005'/>
<id>urn:sha1:3df212576e8b6fb94f8e4b856d39853557d22005</id>
<content type='text'>
[why]
As recommended by DP specs, source needs to make sure
DPRX exits previous LT mode before configuring new LT params
Nofity what channel coding mode we will use for current link training.

Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Initial DC support for Beige Goby</title>
<updated>2021-05-20T02:42:00Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2021-03-15T18:55:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cd6d421e3d1ad5926b74091254e345db730e7706'/>
<id>urn:sha1:cd6d421e3d1ad5926b74091254e345db730e7706</id>
<content type='text'>
[Why&amp;How]
Add Beige Goby (DCN303) resource, irq service, &amp; dmub loader.

v2: fix nbio include (Alex)

Signed-off-by: Chris Park &lt;Chris.Park@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: consider channel coding in configure lttpr mode</title>
<updated>2021-05-20T02:39:13Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2021-05-03T22:42:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f1900a9b0f6436153e6b1be398d31f1ead6096f6'/>
<id>urn:sha1:f1900a9b0f6436153e6b1be398d31f1ead6096f6</id>
<content type='text'>
[why]
Some lttpr configuration steps are exclusive to 8b/10b channel
coding mode. We need to take channel conding into account.

Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Acked-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: minor dp link training refactor</title>
<updated>2021-05-10T22:10:42Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2021-04-13T22:44:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ebc22cbdc058d474210343ec87955711546183ad'/>
<id>urn:sha1:ebc22cbdc058d474210343ec87955711546183ad</id>
<content type='text'>
[how]
The change includes some dp link training refactors:
1. break down is_ch_eq_done to checking individual conditions in
its own function.
2. update dpcd_set_training_pattern to take in dc_dp_training_pattern
as input.
3. moving lttpr mode struct definition into link_service_types.h

Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add fallback and abort paths for DP link training.</title>
<updated>2021-05-10T22:10:00Z</updated>
<author>
<name>Jimmy Kizito</name>
<email>Jimmy.Kizito@amd.com</email>
</author>
<published>2021-04-07T22:56:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8225367130666bf2961399a85913af1b4497d9b4'/>
<id>urn:sha1:8225367130666bf2961399a85913af1b4497d9b4</id>
<content type='text'>
[Why]
When enabling a DisplayPort stream:
- Optionally reducing link bandwidth between failed link training
attempts should progressively relax training requirements.
- Abandoning link training altogether if a sink is unplugged should
avoid unnecessary training attempts.

[How]
- Add fallback parameter to DP link training function and reduce link
bandwidth between failed training attempts as long as stream bandwidth
requirements are met.
- Add training status for sink unplug and abort training when this
status is reported.

Signed-off-by: Jimmy Kizito &lt;Jimmy.Kizito@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
