<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/include, branch v5.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-07-18T19:17:20Z</updated>
<entry>
<title>drm/amd/display: handle active dongle port type is DP++ or DP case</title>
<updated>2019-07-18T19:17:20Z</updated>
<author>
<name>Dale Zhao</name>
<email>dale.zhao@amd.com</email>
</author>
<published>2019-07-10T09:36:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b70666934b41c081489d5ff3c5bf017796545d35'/>
<id>urn:sha1:b70666934b41c081489d5ff3c5bf017796545d35</id>
<content type='text'>
[Why]:
Some active dongles have DP++ port and DP port at the same time. Current
code doesn't cover DP++ case and processes as default DVI case, in which
audio is disabled. Because of dual mode, DP case is also treat as DVI case
for the other port.

[How]:
According DP 1.4 spec, add DP++ procedure similar with HDMI case. Also
add None dongle type for DP case.

Signed-off-by: Dale Zhao &lt;dale.zhao@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy</title>
<updated>2019-06-22T14:34:13Z</updated>
<author>
<name>Wenjing Liu</name>
<email>Wenjing.Liu@amd.com</email>
</author>
<published>2019-05-16T17:01:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=39a4eb853f9ac85e9b042874ef5fa12c8e20e440'/>
<id>urn:sha1:39a4eb853f9ac85e9b042874ef5fa12c8e20e440</id>
<content type='text'>
[why]
Current policy assumes virtual DPCD peer device as
an individual MST branch device with 1 input and 1 output.
However this is only true for virtual DP-to-DP peer device.
In general there are three types of virtual DP peer devices.
1. Sink peer device with virtual DPCD.
2. Virtual DP-to-DP Peer device with virtual DPCD.
3. Virtual DP-to-HDMI Protocol Converter Peer Device with
Virtual DPCD.
So we should break the assumption and handle all three types.

[how]
DP-to-DP peer device will have virtual DPCD cap upstream.
Sink peer device will have virtual DPCD on the logical port.
Dp to HDMI protocol converter peer device will have virtual DPCD
on its converter port.
For DSC capable Synaptics non VGA port we workaround by enumerating
a virutal DPCD peer device on its upstream
even if it doesn't have one.

Signed-off-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add dsc_passthrough_support bit in dpcd struct</title>
<updated>2019-06-22T14:34:12Z</updated>
<author>
<name>Wenjing Liu</name>
<email>Wenjing.Liu@amd.com</email>
</author>
<published>2019-04-25T20:24:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=09104d151acfb32e0d6039d8c0f8f59e22af2c46'/>
<id>urn:sha1:09104d151acfb32e0d6039d8c0f8f59e22af2c46</id>
<content type='text'>
Signed-off-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Reviewed-by: Nikola Cornij &lt;Nikola.Cornij@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: [backport] dwb dm + efc support</title>
<updated>2019-06-22T14:34:11Z</updated>
<author>
<name>Charlene Liu</name>
<email>charlene.liu@amd.com</email>
</author>
<published>2019-04-17T23:15:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=72c6473a6aff9112dc213558bbe55b673f56d161'/>
<id>urn:sha1:72c6473a6aff9112dc213558bbe55b673f56d161</id>
<content type='text'>
dwb fixes.

Signed-off-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Reviewed-by: Duke Du &lt;Duke.Du@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Create DWB resource for DCN2</title>
<updated>2019-06-22T14:34:11Z</updated>
<author>
<name>Charlene Liu</name>
<email>charlene.liu@amd.com</email>
</author>
<published>2019-04-30T17:01:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bb21290ff61529f7b8a6acdba6bbc21b15ac8c18'/>
<id>urn:sha1:bb21290ff61529f7b8a6acdba6bbc21b15ac8c18</id>
<content type='text'>
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.

Signed-off-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Duke Du &lt;Duke.Du@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support for extended DSC DPCD caps</title>
<updated>2019-06-22T14:34:11Z</updated>
<author>
<name>Nikola Cornij</name>
<email>nikola.cornij@amd.com</email>
</author>
<published>2019-04-17T23:07:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f446489adcbc9c4833ae724a985166731c577bcd'/>
<id>urn:sha1:f446489adcbc9c4833ae724a985166731c577bcd</id>
<content type='text'>
[why]
A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order
to give DSC branch decoders a chance to expose their maximum throughput
and maximum line width limitations.

Signed-off-by: Nikola Cornij &lt;nikola.cornij@amd.com&gt;
Reviewed-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DSC support for Navi (v2)</title>
<updated>2019-06-22T14:34:07Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2019-02-25T18:26:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=97bda0322b8a91aa8d534763e709571b2334e585'/>
<id>urn:sha1:97bda0322b8a91aa8d534763e709571b2334e585</id>
<content type='text'>
Add support for DCN2 DSC (Display Stream Compression)

HW Blocks:

 +--------++------+       +----------+
 | HUBBUB || HUBP |  &lt;--  | MMHUBBUB |
 +--------++------+       +----------+
        |                     ^
        v                     |
    +--------+            +--------+
    |  DPP   |            |  DWB   |
    +--------+            +--------+
        |
        v                      ^
    +--------+                 |
    |  MPC   |                 |
    +--------+                 |
        |                      |
        v                      |
    +-------+      +-------+   |
    |  OPP  | &lt;--&gt; |  DSC  |   |
    +-------+      +-------+   |
        |                      |
        v                      |
    +--------+                /
    |  OPTC  |  --------------
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+

v2: rebase (Alex)

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN2 and NV ASIC ID</title>
<updated>2019-06-21T23:59:34Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2019-02-22T15:11:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9793014570b90340adf464f7af45f15adb436c63'/>
<id>urn:sha1:9793014570b90340adf464f7af45f15adb436c63</id>
<content type='text'>
DCN2.0 (Display Core Next) is the display block in Navi10.

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: make clk mgr soc specific</title>
<updated>2019-05-31T15:39:29Z</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2019-04-22T23:39:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dc88b4a684d284a200c0ecfd8d87179d6f6c89a3'/>
<id>urn:sha1:dc88b4a684d284a200c0ecfd8d87179d6f6c89a3</id>
<content type='text'>
[Why]
First step of refactoring clk mgr to better handle different
ways of handling clock operations. Clock operation policies are
soc specific and not just DCN vesion specific. It is not a hw resource,
should not be in the resource pool.

[How]
Change clock manager creation to be based on HW internal ID, rename
clock manager members to be more clear. Move clock manager out of
resource.

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Drop DCN1_01 guards</title>
<updated>2019-05-24T17:20:59Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2019-05-14T13:12:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=97df424fe7a7497a129f057527f646c91b881fbf'/>
<id>urn:sha1:97df424fe7a7497a129f057527f646c91b881fbf</id>
<content type='text'>
[WHY]
These were only needed for bringup. They're not needed anymore.

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
