linux/drivers/gpu/drm/amd/display/include, branch v6.0

drm/amd/display: add chip revision to DCN32

2022-08-16T22:09:25Z

[Why & How] Add GC_11_0_3_A0 as a chip revision to the DCN32 family Reviewed-by: Rodrigo Siqueira Acked-by: Brian Chang Signed-off-by: Samson Tam Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add reserved dc_log_type.

2022-08-16T22:07:28Z

Reviewed-by: Anthony Koo Acked-by: Brian Chang Signed-off-by: Ian Chen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: change family id name for DCN314

2022-08-10T19:10:12Z

GC version is 11.0.1 rather than 11.0.2 Signed-off-by: Yifan Zhang Reviewed-by: Roman Li Signed-off-by: Alex Deucher

drm/amd/display: Add DCN314 version identifiers

2022-07-14T00:57:05Z

DCN 3.1.4 version and family ids Signed-off-by: Roman Li Signed-off-by: Alex Deucher

drm/amd/display: OVT Update on InfoFrame and Mode Management

2022-07-05T20:17:20Z

[Why] Integrate OVT timing from DM to DC logic to update info frame and mode management to report the resolution to the OS. [How] Reflect RID and Frame Rate to AVI InfoFrame Version 5. Define new Timing Standard for OVT timing. Reviewed-by: Charlene Liu Acked-by: Alan Liu Signed-off-by: Chris Park Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: rename lane_settings to hw_lane_settings

2022-06-21T22:17:23Z

[why] This is one of the major steps to decouple hw lane settings from dpcd lane settings. Tested-by: Daniel Wheeler Reviewed-by: Jun Lei Acked-by: Alan Liu Signed-off-by: Wenjing Liu Signed-off-by: Alex Deucher

drm/amd/display: Remove compiler warning

2022-06-21T22:17:22Z

Tested-by: Daniel Wheeler Reviewed-by: Aric Cyr Acked-by: Rodrigo Siqueira Signed-off-by: Cruise Hung Signed-off-by: Alex Deucher

drm/amd/display: lower lane count first when CR done partially fails in EQ

2022-06-15T01:38:40Z

[why] According to DP specs, in EQ DONE phase of link training, we should lower lane count when at least one CR DONE bit is set to 1, while lower link rate when all CR DONE bits are 0s. However in our code, we will treat both cases as latter. This is not exactly correct based on the specs expectation. [how] Check lane0 CR DONE bit when it is still set but CR DONE fails, we treat it as a partial CR DONE failure in EQ DONE phase, we will follow the same fallback flow as when ED DONE fails in EQ DONE phase. Reviewed-by: George Shen Acked-by: Hamza Mahfooz Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove duplicated macro

2022-06-08T15:40:11Z

Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support

2022-06-07T20:09:57Z

[why & how] Expose vendor specific DPCD registers for rate controlling the eDP sink TCON's refresh rate during PSR active. When used in combination with PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for short. v2: Add all DPCD registers required Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher