<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/modules/freesync/freesync.c, branch v5.12</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.12</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.12'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-12-09T04:03:04Z</updated>
<entry>
<title>drm/amd/display: Set FixRate bit in VSIF V3</title>
<updated>2020-12-09T04:03:04Z</updated>
<author>
<name>AMD\ramini</name>
<email>Reza.Amini@amd.com</email>
</author>
<published>2020-11-24T22:08:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=983bcb4cbe259ca6b2e03a6133364681aff1b88b'/>
<id>urn:sha1:983bcb4cbe259ca6b2e03a6133364681aff1b88b</id>
<content type='text'>
[Why]
Signal FreeSync display that we are in Fixed Rate mode, and
expand the FreeSync range to 1024.

[How]
Set the new bit in SB16:bit0, and augment the min and max
refresh rate with 2 extra bits.

Signed-off-by: AMD\ramini &lt;Reza.Amini@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Implement VSIF V3 extended refresh rate feature</title>
<updated>2020-12-09T04:02:57Z</updated>
<author>
<name>Reza Amini</name>
<email>Reza.Amini@amd.com</email>
</author>
<published>2020-07-09T22:01:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9bc41626658271de26cd9086c6e82811ca334dd2'/>
<id>urn:sha1:9bc41626658271de26cd9086c6e82811ca334dd2</id>
<content type='text'>
[Why]
Implement feature of VSIF V3

[How]
Set refresh rate MSB for extended range

Signed-off-by: Reza Amini &lt;Reza.Amini@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: FreeSync not active near lower bound of non-LFC monitor range</title>
<updated>2020-10-05T19:17:05Z</updated>
<author>
<name>Aric Cyr</name>
<email>aric.cyr@amd.com</email>
</author>
<published>2020-09-23T01:37:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5dff371a7351a7e9cbb06bca9e532db16594c053'/>
<id>urn:sha1:5dff371a7351a7e9cbb06bca9e532db16594c053</id>
<content type='text'>
[Why]
On narrow range monitors without LFC, a margin prevents good utilization
of the available range.

[How]
Decrease the margin for exiting fixed mode and fix the frame counter to
reset if a non-consecutive render is found.

Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fixed comments (uniform style)</title>
<updated>2020-10-05T19:16:20Z</updated>
<author>
<name>Felipe</name>
<email>Felipe.Clark@amd.com</email>
</author>
<published>2020-09-03T15:06:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fe984cb3dd325c4c5c7c360e43d93608d4d8870a'/>
<id>urn:sha1:fe984cb3dd325c4c5c7c360e43d93608d4d8870a</id>
<content type='text'>
[WHY]
This change was implemented because the comment style was not uniform
across the file. In some lines comments were initiated with // and in
others they were in between /* ... */.
Additionally, the style for multi-line comments was also not uniform and
some comment lines were missing the space between the opening /* and the
first word of the comment.

[HOW]
All comments are now in between /*.../*, multi line comments also use
/*...*/ and for every comment there is now a space between the opening
/* and the first word of the comment.

Signed-off-by: Felipe &lt;Felipe.Clark@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix LFC multiplier changing erratically</title>
<updated>2020-08-10T22:08:53Z</updated>
<author>
<name>Anthony Koo</name>
<email>Anthony.Koo@amd.com</email>
</author>
<published>2020-07-29T21:33:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e4ed4dbbc8383d42a197da8fe7ca6434b0f14def'/>
<id>urn:sha1:e4ed4dbbc8383d42a197da8fe7ca6434b0f14def</id>
<content type='text'>
[Why]
1. There is a calculation that is using frame_time_in_us instead of
last_render_time_in_us to calculate whether choosing an LFC multiplier
would cause the inserted frame duration to be outside of range.

2. We do not handle unsigned integer subtraction correctly and it underflows
to a really large value, which causes some logic errors.

[How]
1. Fix logic to calculate 'within range' using last_render_time_in_us
2. Split out delta_from_mid_point_delta_in_us calculation to ensure
we don't underflow and wrap around

Signed-off-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Allow asic specific FSFT timing optimization</title>
<updated>2020-08-06T20:40:18Z</updated>
<author>
<name>Reza Amini</name>
<email>Reza.Amini@amd.com</email>
</author>
<published>2020-07-15T15:33:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=471c1dd9546df81d259664ac3e2ab0e99169f755'/>
<id>urn:sha1:471c1dd9546df81d259664ac3e2ab0e99169f755</id>
<content type='text'>
[Why]
Each asic can optimize best based on its capabilities

[How]
Optimizing timing for a new pixel clock

Signed-off-by: Reza Amini &lt;Reza.Amini@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Implement AMD VSIF V3</title>
<updated>2020-07-21T19:37:39Z</updated>
<author>
<name>Reza Amini</name>
<email>Reza.Amini@amd.com</email>
</author>
<published>2020-07-02T20:10:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=831010da1b0b8f0d3e8a5ae4dc81b09947de38f7'/>
<id>urn:sha1:831010da1b0b8f0d3e8a5ae4dc81b09947de38f7</id>
<content type='text'>
[Why]
To support V3

[How]
Generate new VSIF for V3

Signed-off-by: Reza Amini &lt;Reza.Amini@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Send VSIF on unsupported modes on DAL</title>
<updated>2020-07-08T13:01:45Z</updated>
<author>
<name>Jaehyun Chung</name>
<email>jaehyun.chung@amd.com</email>
</author>
<published>2020-06-23T22:30:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=486b7680465e931d02075cbb8f6af1ac9ef48fd2'/>
<id>urn:sha1:486b7680465e931d02075cbb8f6af1ac9ef48fd2</id>
<content type='text'>
[Why]
Current DAL behaviour is to not send VSIF if mode does not support VRR
(ie. FS range is &lt; 10Hz). However, we should still set FS Native Color
Active bit in some unsupported mode cases.

[How]
Remove check for if VRR is supported before building infopacket.

Signed-off-by: Jaehyun Chung &lt;jaehyun.chung@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix incorrect rounding for 10Hz refresh range</title>
<updated>2020-07-02T16:02:54Z</updated>
<author>
<name>Jaehyun Chung</name>
<email>jaehyun.chung@amd.com</email>
</author>
<published>2020-06-18T19:27:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ad339f69114a6a145fc94d44376851c53dee3475'/>
<id>urn:sha1:ad339f69114a6a145fc94d44376851c53dee3475</id>
<content type='text'>
[Why]
In cases where refresh range is slightly below 10, FreeSync is not
active or supported. Need to round values before checking refresh range
in order to have FreeSync supported in these cases.

[How]
Remove redundant values and round values before checking valid refresh range.

Signed-off-by: Jaehyun Chung &lt;jaehyun.chung@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Change infopacket type programming</title>
<updated>2020-04-22T22:11:47Z</updated>
<author>
<name>Haiyi Zhou</name>
<email>haiyi.zhou@amd.com</email>
</author>
<published>2020-04-03T14:00:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d2bacc38f6caa96e6d67d2e3e2bd0aee36de6954'/>
<id>urn:sha1:d2bacc38f6caa96e6d67d2e3e2bd0aee36de6954</id>
<content type='text'>
[Why]
Certain displays may experience blanking if infopacket max range does
not equal nominal refresh rate.

[How]
Add additional infopacket versions to program range to full or forced
range in freesync states.
This does not change the vrr logic.

Signed-off-by: Haiyi Zhou &lt;haiyi.zhou@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
