<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display/modules, branch v5.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-01-07T22:21:20Z</updated>
<entry>
<title>drm/amd/display: unhard code link to phy idx mapping in dc link and clean up</title>
<updated>2022-01-07T22:21:20Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2021-12-13T23:29:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=580013b2cef8babc204b7b78ff093140e112b194'/>
<id>urn:sha1:580013b2cef8babc204b7b78ff093140e112b194</id>
<content type='text'>
[why]
1. Current code hard codes link to PHY mapping in dc link level per asic
per revision.
This is not scalable. In long term the mapping will be obatined from
DMUB and store in dc resource.

2. Depending on DCN revision and endpoint type, the definition of
dio_output_idx dio_output_type and phy_idx are not  consistent. We need
to unify the meaning of these hardware indices across different system
configuration.

[how]
1. Temporarly move the hardcoded mapping to dc_resource level, which
should have full awareness of asic specific configuration and add a TODO
comment to move the mapping to DMUB.

2. populate dio_output_idx/phy_idx for all configuration, define
usb4_enabled bit instead of dio_output_type as an external enum.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix deadlock when falling back to v2 from v3</title>
<updated>2021-10-28T18:26:51Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-10-22T20:14:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f638d7505f99bca9436aac37b2a1ecb3f84803a5'/>
<id>urn:sha1:f638d7505f99bca9436aac37b2a1ecb3f84803a5</id>
<content type='text'>
[Why]
A deadlock in the kernel occurs when we fallback from the V3 to V2
add_topology_to_display or remove_topology_to_display because they
both try to acquire the dtm_mutex but recursive locking isn't
supported on mutex_lock().

[How]
Make the mutex_lock/unlock more fine grained and move them up such that
they're only required for the psp invocation itself.

Fixes: bf62221e9d0e ("drm/amd/display: Add DCN3.1 HDCP support")

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1</title>
<updated>2021-10-28T18:26:14Z</updated>
<author>
<name>Ahmad Othman</name>
<email>ahmad.Othman@amd.com</email>
</author>
<published>2021-10-06T01:04:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ffd89aa968d9046ab5fb9f7cdb7f8d3c383a15c1'/>
<id>urn:sha1:ffd89aa968d9046ab5fb9f7cdb7f8d3c383a15c1</id>
<content type='text'>
[Why]
Created new fields that matches new B0 structs On DCN31 the mapping of
DIO output to PHY differs from A0 to B0 boards with new PHY C20 &amp; this
new mapping needed to be handled.

[How]
Mapped new structure based on new structs Added logic for mapping over
A0 and B0 boards Hooked all new structs together.

Reviewed-by: Wenjing Liu &lt;Wenjing.Liu@amd.com&gt;
Acked-by: Agustin Gutierrez &lt;agustin.gutierrez@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Ahmad Othman &lt;Ahmad.Othman@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Get ceiling for v_total calc</title>
<updated>2021-10-28T18:26:14Z</updated>
<author>
<name>Guo, Bing</name>
<email>Bing.Guo@amd.com</email>
</author>
<published>2021-10-04T17:13:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=33df94e181f2181e2bd04c3830eb380f2f3ed048'/>
<id>urn:sha1:33df94e181f2181e2bd04c3830eb380f2f3ed048</id>
<content type='text'>
Updating certain variable blanking calculations to use ceiling function.

Reviewed-by: Chris Park &lt;chris.park@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Acked-by: Agustin Gutierrez &lt;agustin.gutierrez@amd.com&gt;
Signed-off-by: Bing Guo &lt;Bing.Guo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Revert adding degamma coefficients</title>
<updated>2021-09-14T19:57:10Z</updated>
<author>
<name>Jaehyun Chung</name>
<email>jaehyun.chung@amd.com</email>
</author>
<published>2021-08-30T20:46:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9b3d76527f6ea50270f7f7ac749493b41783e8bd'/>
<id>urn:sha1:9b3d76527f6ea50270f7f7ac749493b41783e8bd</id>
<content type='text'>
[Why]
Degamma coefficients are calculated in our degamma formula using
the regamma coefficients. We do not need to add separate degamma
coefficients.

[How]
Remove the change to add separate degamma coefficients.

Reviewed-by: Krunoslav Kovac &lt;Krunoslav.Kovac@amd.com&gt;
Acked-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Signed-off-by: Jaehyun Chung &lt;jaehyun.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Correct degamma coefficients</title>
<updated>2021-09-14T19:57:10Z</updated>
<author>
<name>Jaehyun Chung</name>
<email>jaehyun.chung@amd.com</email>
</author>
<published>2021-08-27T20:10:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1b76cd177288bc2ca6ff05ec244361271151a57d'/>
<id>urn:sha1:1b76cd177288bc2ca6ff05ec244361271151a57d</id>
<content type='text'>
[Why]
Some incorrect coefficients were being used

Reviewed-by: Michael Strauss &lt;michael.strauss@amd.com&gt;
Acked-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Signed-off-by: Jaehyun Chung &lt;jaehyun.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add regamma/degamma coefficients and set sRGB when TF is BT709</title>
<updated>2021-09-14T19:57:10Z</updated>
<author>
<name>Jaehyun Chung</name>
<email>jaehyun.chung@amd.com</email>
</author>
<published>2021-08-24T18:05:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d020970959169627d59a711769f8c4b87bf5f90c'/>
<id>urn:sha1:d020970959169627d59a711769f8c4b87bf5f90c</id>
<content type='text'>
[Why]
In YUV case, need to set the input TF to sRGB instead of BT709,
even though the input TF type is distributed. SRGB was not
being used because pixel format was not being set in the
surface update sequence.
Also, we were using the same coefficients for degamma and
regamma formula, causing the cutoff point of the linear
section of the curve to be incorrect.

[How]
Set pixel format in the surface update sequence. Add separate
coefficient arrays for regamma and degamma.

Reviewed-by: Krunoslav Kovac &lt;Krunoslav.Kovac@amd.com&gt;
Acked-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Signed-off-by: Jaehyun Chung &lt;jaehyun.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: consolidate TA shared memory structures</title>
<updated>2021-08-18T22:22:53Z</updated>
<author>
<name>Candice Li</name>
<email>candice.li@amd.com</email>
</author>
<published>2021-08-16T15:28:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ce97f37be8957a7f3f42eafaa9469b0ab941e63b'/>
<id>urn:sha1:ce97f37be8957a7f3f42eafaa9469b0ab941e63b</id>
<content type='text'>
Signed-off-by: Candice Li &lt;candice.li@amd.com&gt;
Reviewed-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add authentication_complete in hdcp output</title>
<updated>2021-08-09T19:43:33Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2021-07-26T18:59:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0a95fab36a660021c3127476a8df6518fe47a23e'/>
<id>urn:sha1:0a95fab36a660021c3127476a8df6518fe47a23e</id>
<content type='text'>
[why]
DM needs to be notified when hdcp module has completed
authentication attempt.

Reviewed-by: Bhawanpreet Lakha &lt;bhawanpreet.lakha@amd.com&gt;
Reviewed-by: George Shen &lt;George.Shen@amd.com&gt;
Acked-by: Anson Jacob &lt;Anson.Jacob@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove unused functions</title>
<updated>2021-07-28T20:37:17Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2021-07-15T18:55:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7ac851bcd54778337fb500e9c03ae1bd44de4f3d'/>
<id>urn:sha1:7ac851bcd54778337fb500e9c03ae1bd44de4f3d</id>
<content type='text'>
[why]
It has been decided that opm state query support will be dropped.
Therefore link encryption enabled and save current encryption states
won't be used anymore and there are no foreseeable usages in the future.
We will remove these two interfaces for clean up.

Acked-by: Solomon Chiu &lt;solomon.chiu@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
