<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display, branch v5.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-02-23T21:31:06Z</updated>
<entry>
<title>drm/amd/display: Fix stream-&gt;link_enc unassigned during stream removal</title>
<updated>2022-02-23T21:31:06Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2022-01-25T17:04:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3743e7f6fcb938b7d8b7967e6a9442805e269b3d'/>
<id>urn:sha1:3743e7f6fcb938b7d8b7967e6a9442805e269b3d</id>
<content type='text'>
[Why]
Found when running igt@kms_atomic.

Userspace attempts to do a TEST_COMMIT when 0 streams which calls
dc_remove_stream_from_ctx. This in turn calls link_enc_unassign
which ends up modifying stream-&gt;link = NULL directly, causing the
global link_enc to be removed preventing further link activity
and future link validation from passing.

[How]
We take care of link_enc unassignment at the start of
link_enc_cfg_link_encs_assign so this call is no longer necessary.

Fixes global state from being modified while unlocked.

Reviewed-by: Jimmy Kizito &lt;Jimmy.Kizito@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: For vblank_disable_immediate, check PSR is really used</title>
<updated>2022-02-21T22:55:17Z</updated>
<author>
<name>Michel Dänzer</name>
<email>mdaenzer@redhat.com</email>
</author>
<published>2022-02-15T18:53:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4d22336f903930eb94588b939c310743a3640276'/>
<id>urn:sha1:4d22336f903930eb94588b939c310743a3640276</id>
<content type='text'>
Even if PSR is allowed for a present GPU, there might be no eDP link
which supports PSR.

Fixes: 708978487304 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled")
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Michel Dänzer &lt;mdaenzer@redhat.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Protect update_bw_bounding_box FPU code.</title>
<updated>2022-02-21T22:55:17Z</updated>
<author>
<name>Bas Nieuwenhuizen</name>
<email>bas@basnieuwenhuizen.nl</email>
</author>
<published>2022-02-12T15:40:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1432108d00e42ffa383240bcac8d58f89ae19104'/>
<id>urn:sha1:1432108d00e42ffa383240bcac8d58f89ae19104</id>
<content type='text'>
For DCN3/3.01/3.02 at least these use the fpu.

v2: squash in build fix for when DCN is not enabled (Leo)

Signed-off-by: Bas Nieuwenhuizen &lt;bas@basnieuwenhuizen.nl&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/display: change pipe policy for DCN 2.0</title>
<updated>2022-02-09T22:20:47Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-02-03T15:04:58Z</published>
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<id>urn:sha1:6e7545ddb13416fd200e0b91c0acfd0404e2e27b</id>
<content type='text'>
Fixes hangs on driver load with multiple displays on
DCN 2.0 parts.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215511
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1877
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1886
Fixes: ee2698cf79cc ("drm/amd/display: Changed pipe split policy to allow for multi-display pipe split")
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: keep eDP Vdd on when eDP stream is already enabled</title>
<updated>2022-02-09T20:12:03Z</updated>
<author>
<name>Zhan Liu</name>
<email>Zhan.Liu@amd.com</email>
</author>
<published>2022-01-28T03:08:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ad787771b43602d64e02b5963f4192232b46366b'/>
<id>urn:sha1:ad787771b43602d64e02b5963f4192232b46366b</id>
<content type='text'>
[Why]
Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will
be cleared to 0 at S3 resume.

[How]
Keep eDP Vdd on when eDP stream is already enabled.

Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Zhan Liu &lt;Zhan.Liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix yellow carp wm clamping</title>
<updated>2022-02-09T20:10:53Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2022-01-27T16:55:49Z</published>
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<id>urn:sha1:60fdf98a774eee244a4e00c34a9e7729b61d0f44</id>
<content type='text'>
Fix clamping to match register field size

Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Cap pflip irqs per max otg number</title>
<updated>2022-02-09T20:09:42Z</updated>
<author>
<name>Roman Li</name>
<email>Roman.Li@amd.com</email>
</author>
<published>2022-02-02T19:30:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=328e34a5ad227399391891d454043e5d73e598d2'/>
<id>urn:sha1:328e34a5ad227399391891d454043e5d73e598d2</id>
<content type='text'>
[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27-&gt;otg1, 28-&gt;otg2...

Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg id.

e.g. if one pipe out of 3(otg#0-2) is fused adev-&gt;mode_info.num_crtc=2
so DM only registers irq_src 26,27.
This is a bug since if pipe#2 remains unfused DM never gets
otg2 pflip interrupt (irq_src=28)
That may results in gfx failure due to pflip timeout.

[How]
Register pflip interrupts per max num of otg instead of num_crtc

Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>display/amd: decrease message verbosity about watermarks table failure</title>
<updated>2022-02-09T20:05:56Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2022-01-25T21:49:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=03ad3093c7c069d6ab4403730009ebafeea9ee37'/>
<id>urn:sha1:03ad3093c7c069d6ab4403730009ebafeea9ee37</id>
<content type='text'>
A number of BIOS versions have a problem with the watermarks table not
being configured properly.  This manifests as a very scary looking warning
during resume from s0i3.  This should be harmless in most cases and is well
understood, so decrease the assertion to a clearer warning about the problem.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Force link_rate as LINK_RATE_RBR2 for 2018 15" Apple Retina panels</title>
<updated>2022-02-02T23:35:00Z</updated>
<author>
<name>Aun-Ali Zaidi</name>
<email>admin@kodeit.net</email>
</author>
<published>2022-01-29T05:49:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=30fbce374745a9c6af93c775a5ac49a97f822fda'/>
<id>urn:sha1:30fbce374745a9c6af93c775a5ac49a97f822fda</id>
<content type='text'>
The eDP link rate reported by the DP_MAX_LINK_RATE dpcd register (0xa) is
contradictory to the highest rate supported reported by
EDID (0xc = LINK_RATE_RBR2). The effects of this compounded with commit
'4a8ca46bae8a ("drm/amd/display: Default max bpc to 16 for eDP")' results
in no display modes being found and a dark panel.

For now, simply force the maximum supported link rate for the eDP attached
2018 15" Apple Retina panels.

Additionally, we must also check the firmware revision since the device ID
reported by the DPCD is identical to that of the more capable 16,1,
incorrectly quirking it. We also use said firmware check to quirk the
refreshed 15,1 models with Vega graphics as they use a slightly newer
firmware version.

Tested-by: Aun-Ali Zaidi &lt;admin@kodeit.net&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Aun-Ali Zaidi &lt;admin@kodeit.net&gt;
Signed-off-by: Aditya Garg &lt;gargaditya08@live.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: revert "Reset fifo after enable otg"</title>
<updated>2022-02-02T23:35:00Z</updated>
<author>
<name>Zhan Liu</name>
<email>Zhan.Liu@amd.com</email>
</author>
<published>2022-01-28T14:03:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=49a6ebb95d04bdaa5d57313a380c44249cf02100'/>
<id>urn:sha1:49a6ebb95d04bdaa5d57313a380c44249cf02100</id>
<content type='text'>
[Why]
This change causes regression, that prevents some systems
from lighting up internal displays.

[How]
Revert this patch until a new solution is ready.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Signed-off-by: Zhan Liu &lt;Zhan.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
</feed>
