<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/display, branch v6.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-04-18T21:20:00Z</updated>
<entry>
<title>drm/amd/display: fix a divided-by-zero error</title>
<updated>2023-04-18T21:20:00Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2023-04-03T09:45:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0b5dfe12755f87ec014bb4cc1930485026167430'/>
<id>urn:sha1:0b5dfe12755f87ec014bb4cc1930485026167430</id>
<content type='text'>
[Why &amp; How]

timing.dsc_cfg.num_slices_v can be zero and it is necessary to check
before using it.

This fixes the error "divide error: 0000 [#1] PREEMPT SMP NOPTI".

Reviewed-by: Aurabindo Pillai &lt;Aurabindo.Pillai@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: limit timing for single dimm memory</title>
<updated>2023-04-18T21:17:59Z</updated>
<author>
<name>Daniel Miess</name>
<email>Daniel.Miess@amd.com</email>
</author>
<published>2023-04-04T18:04:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1e994cc0956b8dabd1b1fef315bbd722733b8aa8'/>
<id>urn:sha1:1e994cc0956b8dabd1b1fef315bbd722733b8aa8</id>
<content type='text'>
[Why]
1. It could hit bandwidth limitdation under single dimm
memory when connecting 8K external monitor.
2. IsSupportedVidPn got validation failed with
2K240Hz eDP + 8K24Hz external monitor.
3. It's better to filter out such combination in
EnumVidPnCofuncModality
4. For short term, filter out in dc bandwidth validation.

[How]
Force 2K@240Hz+8K@24Hz timing validation false in dc.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Daniel Miess &lt;Daniel.Miess@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: set dcn315 lb bpp to 48</title>
<updated>2023-04-18T21:16:35Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2023-04-03T14:13:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6d9240c46f7419aa3210353b5f52cc63da5a6440'/>
<id>urn:sha1:6d9240c46f7419aa3210353b5f52cc63da5a6440</id>
<content type='text'>
[Why &amp; How]
Fix a typo for dcn315 line buffer bpp.

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix desktop freezed after gpu-reset</title>
<updated>2023-04-18T21:14:13Z</updated>
<author>
<name>Alan Liu</name>
<email>HaoPing.Liu@amd.com</email>
</author>
<published>2023-04-14T10:39:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c8b5a95b570949536a2b75cd8fc4f1de0bc60629'/>
<id>urn:sha1:c8b5a95b570949536a2b75cd8fc4f1de0bc60629</id>
<content type='text'>
[Why]
After gpu-reset, sometimes the driver fails to enable vblank irq,
causing flip_done timed out and the desktop freezed.

During gpu-reset, we disable and enable vblank irq in dm_suspend() and
dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we check
irqs' refcount and decide to enable or disable the irqs again.

However, we have 2 sets of API for controling vblank irq, one is
dm_vblank_get/put() and another is amdgpu_irq_get/put(). Each API has
its own refcount and flag to store the state of vblank irq, and they
are not synchronized.

In drm we use the first API to control vblank irq but in
amdgpu_irq_gpu_reset_resume_helper() we use the second set of API.

The failure happens when vblank irq was enabled by dm_vblank_get()
before gpu-reset, we have vblank-&gt;enabled true. However, during
gpu-reset, in amdgpu_irq_gpu_reset_resume_helper() vblank irq's state
checked from amdgpu_irq_update() is DISABLED. So finally it disables
vblank irq again. After gpu-reset, if there is a cursor plane commit,
the driver will try to enable vblank irq by calling drm_vblank_enable(),
but the vblank-&gt;enabled is still true, so it fails to turn on vblank
irq and causes flip_done can't be completed in vblank irq handler and
desktop become freezed.

[How]
Combining the 2 vblank control APIs by letting drm's API finally calls
amdgpu_irq's API, so the irq's refcount and state of both APIs can be
synchronized. Also add a check to prevent refcount from being less then
0 in amdgpu_irq_put().

v2:
- Add warning in amdgpu_irq_enable() if the irq is already disabled.
- Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change
  if it is in gpu-reset.

v3:
- Improve commit message and code comments.

Signed-off-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Pass the right info to drm_dp_remove_payload</title>
<updated>2023-04-12T20:11:17Z</updated>
<author>
<name>Wayne Lin</name>
<email>Wayne.Lin@amd.com</email>
</author>
<published>2023-02-17T05:26:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b8ca445f550a9a079134f836466ddda3bfad6108'/>
<id>urn:sha1:b8ca445f550a9a079134f836466ddda3bfad6108</id>
<content type='text'>
[Why &amp; How]
drm_dp_remove_payload() interface was changed. Correct amdgpu dm code
to pass the right parameter to the drm helper function.

Reviewed-by: Jerry Zuo &lt;Jerry.Zuo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Take FEC Overhead into Timeslot Calculation</title>
<updated>2023-03-29T21:21:06Z</updated>
<author>
<name>Fangzhi Zuo</name>
<email>Jerry.Zuo@amd.com</email>
</author>
<published>2023-03-01T02:34:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=68dc1846c3a44d5e633be145c169ce2fd5420695'/>
<id>urn:sha1:68dc1846c3a44d5e633be145c169ce2fd5420695</id>
<content type='text'>
8b/10b encoding needs to add 3% fec overhead into the pbn.
In the Synapcis Cascaded MST hub, the first stage MST branch device
needs the information to determine the timeslot count for the
second stage MST branch device. Missing this overhead will leads to
insufficient timeslot allocation.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DSC Support for Synaptics Cascaded MST Hub</title>
<updated>2023-03-29T21:21:05Z</updated>
<author>
<name>Fangzhi Zuo</name>
<email>Jerry.Zuo@amd.com</email>
</author>
<published>2023-02-24T18:45:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f4f3b7dedbe849e780c779ba67365bb1db0d8637'/>
<id>urn:sha1:f4f3b7dedbe849e780c779ba67365bb1db0d8637</id>
<content type='text'>
Traditional synaptics hub has one MST branch device without virtual dpcd.
Synaptics cascaded hub has two chained MST branch devices. DSC decoding
is performed via root MST branch device, instead of the second MST branch
device.

Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Set dcn32 caps.seamless_odm</title>
<updated>2023-03-23T13:39:34Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2023-03-09T20:58:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe'/>
<id>urn:sha1:f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe</id>
<content type='text'>
[Why &amp; How]
seamless_odm set was not picked up while
merging commit 2d017189e2b3 ("drm/amd/display:
Blank eDP on enable drv if odm enabled")

Fixes: 2d017189e2b3 ("drm/amd/display: Blank eDP on enable drv if odm enabled")
Reviewed-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk</title>
<updated>2023-03-23T13:39:34Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2023-03-09T21:14:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4c94e57c258cb7800aa5f3a9d9597d91291407a9'/>
<id>urn:sha1:4c94e57c258cb7800aa5f3a9d9597d91291407a9</id>
<content type='text'>
[Why &amp; How]
When merging commit 9af611f29034
("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming"),
index change was not picked up.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Fixes: 9af611f29034 ("drm/amd/display: Fix DCN32 DPSTREAMCLK_CNTL programming")
Reviewed-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove outdated 8bpc comments</title>
<updated>2023-03-23T13:34:07Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2023-03-06T03:39:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6d457ca162da98a6a1a381320e936d7448177de9'/>
<id>urn:sha1:6d457ca162da98a6a1a381320e936d7448177de9</id>
<content type='text'>
[Why]
The commit c76e483cd916 ("drm/amd/display: Don't restrict bpc to 8 bpc")
removes the historical 8bpc dependency and sets max_bpc to 16.

[How]
The comment that states "8bpc for non-edp" needs to be removed as well.

Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
