<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include/amd_shared.h, branch v5.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-12-13T21:32:34Z</updated>
<entry>
<title>drm/amd/display: Add feature flags to disable LTTPR</title>
<updated>2021-12-13T21:32:34Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2021-12-07T17:14:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=123202744955e62470174fc3ba666a4d98062ea6'/>
<id>urn:sha1:123202744955e62470174fc3ba666a4d98062ea6</id>
<content type='text'>
[Why]
Allow for disabling non transparent mode of LTTPR for running tests.

[How]
Add a feature flag and set them during init sequence. The flags are
already being used in DC.

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: avoid duplicate powergate/ungate setting</title>
<updated>2021-11-22T19:45:02Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2021-11-05T07:25:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6c08e0ef87b8b4c1c243719a561c354e893c415d'/>
<id>urn:sha1:6c08e0ef87b8b4c1c243719a561c354e893c415d</id>
<content type='text'>
Just bail out if the target IP block is already in the desired
powergate/ungate state. This can avoid some duplicate settings
which sometimes may cause unexpected issues.

Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Tested-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable PSR by default on newer DCN</title>
<updated>2021-10-13T18:14:34Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-10-05T14:55:57Z</published>
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<id>urn:sha1:9470620e99e90999dc367bdcccc7e1274dcbb796</id>
<content type='text'>
[Why]
For optimal power savings on panels that can support it.

This was previously left disabled by default because of issues with
compositors that do not pageflip and scan out directly to the
frontbuffer.

For these compositors we now have detection methods that wait for x
number of pageflips after a full update - triggered by a buffer or
format change typically.

This may introduce bugs or new cases not tested by users so this is
only currently targeting newer DCN.

[How]
Add code in DM to set PSR state by default for newer DCN while falling
back to the feature mask for older.

Add a global debug flag that can be set to disable it for either.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add cyan_skillfish asic type</title>
<updated>2021-07-23T14:08:00Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2021-07-13T21:13:48Z</published>
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<id>urn:sha1:d0f56dc25afba6e08be2d2611d5d19f97821aa64</id>
<content type='text'>
Add cyan_skillfish asic family.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enabling eDP no power sequencing with DAL feature mask</title>
<updated>2021-06-30T03:41:22Z</updated>
<author>
<name>Zhan Liu</name>
<email>zhan.liu@amd.com</email>
</author>
<published>2021-06-14T18:54:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a51482458dafb836dbf7c8ae3200ca8db7348201'/>
<id>urn:sha1:a51482458dafb836dbf7c8ae3200ca8db7348201</id>
<content type='text'>
[Why]
Sometimes, DP receiver chip power-controlled externally by an
Embedded Controller could be treated and used as eDP,
if it drives mobile display. In this case,
we shouldn't be doing power-sequencing, hence we can skip
waiting for T7-ready and T9-ready."

[How]
Added a feature mask to enable eDP no power sequencing feature.

To enable this, set 0x10 flag in amdgpu.dcfeaturemask on
Linux command line.

Signed-off-by: Zhan Liu &lt;zhan.liu@amd.com&gt;
Reviewed-by: Nikola Cornij &lt;Nikola.Cornij@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge drm/drm-next into drm-misc-next</title>
<updated>2021-05-22T05:17:05Z</updated>
<author>
<name>Thomas Zimmermann</name>
<email>tzimmermann@suse.de</email>
</author>
<published>2021-05-22T05:17:05Z</published>
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<id>urn:sha1:304ba5dca49a21e6f4040494c669134787145118</id>
<content type='text'>
Backmerging from drm/drm-next to the patches for AMD devices
for v5.14.

Signed-off-by: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add early fini callback</title>
<updated>2021-05-20T03:48:50Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2021-05-20T03:20:57Z</published>
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<id>urn:sha1:e9669fb7826270bd73554208b49b6353ab3d856f</id>
<content type='text'>
Use it to call disply code dependent on device-&gt;drv_data
before it's set to NULL on device unplug

v5:
Move HW finilization into this callback to prevent MMIO accesses
post cpi remove.

v7:
Split kfd suspend from device exit to expdite HW related
stuff to amdgpu_pci_remove

v8:
Squash previous KFD commit into this commit to avoid compile break.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20210520032057.497334-1-andrey.grodzovsky@amd.com
</content>
</entry>
<entry>
<title>drm/amdgpu: add judgement when add ip blocks (v2)</title>
<updated>2021-05-13T14:46:58Z</updated>
<author>
<name>Likun GAO</name>
<email>Likun.Gao@amd.com</email>
</author>
<published>2021-04-29T06:08:13Z</published>
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<id>urn:sha1:83a0b8639185f40ab7fc9dd291a057150eb9d238</id>
<content type='text'>
Judgement whether to add an sw ip according to the harvest info.

v2: fix indentation (Alex)

Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: enable DCS</title>
<updated>2021-02-09T20:27:57Z</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2021-02-03T10:40:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=680602d6c2d6ac850302b0cf4c03dcc6d9ea0fae'/>
<id>urn:sha1:680602d6c2d6ac850302b0cf4c03dcc6d9ea0fae</id>
<content type='text'>
Enable DCS

V1: Enable Async DCS.
V2: Add the ppfeaturemask bit to enable from the modprobe parameter.
V3:
1. add the flag to skip APU support.
2. remove the hunk for workload selection since
it doesn't impact the function.

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add GFX Fine Grain Clock Gating flag</title>
<updated>2020-11-04T22:08:08Z</updated>
<author>
<name>Jinzhou.Su</name>
<email>Jinzhou.Su@amd.com</email>
</author>
<published>2020-11-03T03:39:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=adf16996362e65ce63b5b5ee628e0876d90c079f'/>
<id>urn:sha1:adf16996362e65ce63b5b5ee628e0876d90c079f</id>
<content type='text'>
Add AMD_CG_SUPPORT_GFX_FGCG for FGCG

Signed-off-by: Jinzhou.Su &lt;Jinzhou.Su@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
