<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include/amd_shared.h, branch v5.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-05-05T20:50:58Z</updated>
<entry>
<title>drm/amdgpu: enable more GFX clockgating features for GC 11.0.0</title>
<updated>2022-05-05T20:50:58Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-04-11T06:39:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=915b5ce774b5d59f90f970f97a7295f12cf898bc'/>
<id>urn:sha1:915b5ce774b5d59f90f970f97a7295f12cf898bc</id>
<content type='text'>
Support more GFX clockgating features(3D_CGCG, 3D_CGLS, MGCG,
FGCG and PERF_CLK).

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add FGCG support</title>
<updated>2022-05-04T14:02:56Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-04-07T13:51:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d6b9a91f5d1bd9f8027dbab1119a3a51f0afed26'/>
<id>urn:sha1:d6b9a91f5d1bd9f8027dbab1119a3a51f0afed26</id>
<content type='text'>
Add the CG flag for Fine Grained Clock Gating.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add ih v6_0 ip block v2</title>
<updated>2022-05-04T13:53:12Z</updated>
<author>
<name>Stanley.Yang</name>
<email>Stanley.Yang@amd.com</email>
</author>
<published>2022-02-22T06:53:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6e02c0ed4bb5c3acdf826442ccc30c12791f42d4'/>
<id>urn:sha1:6e02c0ed4bb5c3acdf826442ccc30c12791f42d4</id>
<content type='text'>
This adds ih v6_0 ip block support.  IH is the
interrupt handler.

Signed-off-by: Stanley.Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: add dc feature mask flags for PSR allow smu and multi-display optimizations</title>
<updated>2022-04-26T15:51:36Z</updated>
<author>
<name>David Zhang</name>
<email>dingchen.zhang@amd.com</email>
</author>
<published>2022-04-25T18:33:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5533347dbb6158b9285c558e3578a48da95912a3'/>
<id>urn:sha1:5533347dbb6158b9285c558e3578a48da95912a3</id>
<content type='text'>
[Why]
Allow for PSR SMU optimization and PSR multiple display optimization.

[How]
Add feature flags of PSR smu optimization and PSR multiple display
optimiztaion, and set them during init sequence. By default, flags
are disabled.

Signed-off-by: David Zhang &lt;dingchen.zhang@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Roman Li &lt;Roman.Li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: expand cg_flags from u32 to u64</title>
<updated>2022-04-08T21:24:24Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-03-25T10:00:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=25faeddcf3c3f31f9f43de5c55f7cbdd13d3ebc7'/>
<id>urn:sha1:25faeddcf3c3f31f9f43de5c55f7cbdd13d3ebc7</id>
<content type='text'>
With this, we can support more CG flags.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: suppress the warning about enum value 'AMD_IP_BLOCK_TYPE_NUM'</title>
<updated>2022-01-25T23:00:32Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-01-20T07:03:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=239d6de307b0dd1d48ec9b935b57531f07f6db11'/>
<id>urn:sha1:239d6de307b0dd1d48ec9b935b57531f07f6db11</id>
<content type='text'>
Suppress the warning below on building htmldocs:
drivers/gpu/drm/amd/include/amd_shared.h:103: warning: Enum value
'AMD_IP_BLOCK_TYPE_NUM' not described in enum 'amd_ip_block_type'

Fixes: 6ee27ee27ba8 ("drm/amd/pm: avoid duplicate powergate/ungate setting")

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: revise the performance level setting APIs</title>
<updated>2022-01-14T22:51:15Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2021-11-25T03:15:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=61d7d0d5adc705f833d8a5dbb596253842486220'/>
<id>urn:sha1:61d7d0d5adc705f833d8a5dbb596253842486220</id>
<content type='text'>
Avoid cross callings which make lock protection enforcement
on amdgpu_dpm_force_performance_level() impossible.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add feature flags to disable LTTPR</title>
<updated>2021-12-13T21:32:34Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2021-12-07T17:14:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=123202744955e62470174fc3ba666a4d98062ea6'/>
<id>urn:sha1:123202744955e62470174fc3ba666a4d98062ea6</id>
<content type='text'>
[Why]
Allow for disabling non transparent mode of LTTPR for running tests.

[How]
Add a feature flag and set them during init sequence. The flags are
already being used in DC.

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: avoid duplicate powergate/ungate setting</title>
<updated>2021-11-22T19:45:02Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2021-11-05T07:25:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6c08e0ef87b8b4c1c243719a561c354e893c415d'/>
<id>urn:sha1:6c08e0ef87b8b4c1c243719a561c354e893c415d</id>
<content type='text'>
Just bail out if the target IP block is already in the desired
powergate/ungate state. This can avoid some duplicate settings
which sometimes may cause unexpected issues.

Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789
Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Tested-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable PSR by default on newer DCN</title>
<updated>2021-10-13T18:14:34Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-10-05T14:55:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9470620e99e90999dc367bdcccc7e1274dcbb796'/>
<id>urn:sha1:9470620e99e90999dc367bdcccc7e1274dcbb796</id>
<content type='text'>
[Why]
For optimal power savings on panels that can support it.

This was previously left disabled by default because of issues with
compositors that do not pageflip and scan out directly to the
frontbuffer.

For these compositors we now have detection methods that wait for x
number of pageflips after a full update - triggered by a buffer or
format change typically.

This may introduce bugs or new cases not tested by users so this is
only currently targeting newer DCN.

[How]
Add code in DM to set PSR state by default for newer DCN while falling
back to the feature mask for older.

Add a global debug flag that can be set to disable it for either.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
