linux/drivers/gpu/drm/amd/include/asic_reg/dcn, branch masterMirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=master2026-03-23T18:13:32Zdrm/amd/display: Update underflow detection for DCN422026-03-23T18:13:32ZRoman LiRoman.Li@amd.com2026-03-17T00:17:57Zurn:sha1:c096932fd4f72f89fed0b80df473f3af8217d818
[Why]
The DCN42 underflow detection functions in dcn42_optc.c use
OPTC_RSMU_UNDERFLOW register but the register offset definitions
were missing from dcn_4_2_0_offset.h and dcn42_resource.h.
[How]
Add missing register definitions.
Fixes: e56e3cff2a1b ("drm/amd/display: Sync dcn42 with DC 3.2.373")
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Sync dcn42 with DC 3.2.3732026-03-11T17:58:07ZRoman LiRoman.Li@amd.com2026-03-05T17:56:09Zurn:sha1:e56e3cff2a1bb29545ddbec562e76c0419363a40
This patch provides a bulk merge to align driver
support for DCN42 with Display Core version 3.2.373.
It includes upgrade for:
- clk_mgr
- dml2/dml21
- optc
- hubp
- mpc
- optc
- hwseq
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add dcn42 register headers2026-02-23T19:28:32ZRoman LiRoman.Li@amd.com2026-02-02T22:11:43Zurn:sha1:2214b716a4bdae0dcaa5f08a190396dec9d8ef2f
Register headers for the following IPs:
- DCN 4.2.0
- DPCS 4.0.0
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add some missing register headers for DCN4012025-05-28T20:01:50ZAurabindo Pillaiaurabindo.pillai@amd.com2025-05-21T19:59:56Zurn:sha1:d78eb800f8f5169db89a28380631aefc224a76bb
Add some HDCP related register headers for future use.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add dcn36 register header files2025-02-13T02:04:07ZWayne LinWayne.Lin@amd.com2025-01-10T12:10:34Zurn:sha1:9b194af117a85a603321a3834636f1a8195a2c35
[Why & How]
Add register headers for DCN36.
V2: adjust copyright license text
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: rename register headers to dcn_2_0_12024-12-10T15:37:34ZLeo Lisunpeng.li@amd.com2024-12-05T20:43:42Zurn:sha1:ecc5278ce05d18fb0a2e167ead91394356cb4c79
They were named with the incorrect dcn version.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Sun peng Li <sunpeng.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add a missing DCN401 reg definition2024-11-04T16:40:21ZAurabindo Pillaiaurabindo.pillai@amd.com2024-11-01T16:16:18Zurn:sha1:c7b4ecc1fa29235e5a14ad178ab96ef15a0d16f6
Add a mising reg field to the autogenerated header for future use
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add some missing register definitions2024-06-27T21:32:17ZAurabindo Pillaiaurabindo.pillai@amd.com2024-06-25T18:17:46Zurn:sha1:ad89e904e3aaa93628785546034ec77f3100cf79
Add some register offsets that are required for Display DCC on DCN401
Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add reg definitions for DCN401 DCC2024-06-27T21:10:38ZAurabindo Pillaiaurabindo.pillai@amd.com2024-06-14T19:42:55Zurn:sha1:2d072b445622b90f8a961c0376887120da75221f
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add missing registers for DCN4012024-05-29T18:40:39ZRodrigo SiqueiraRodrigo.Siqueira@amd.com2024-05-17T19:10:20Zurn:sha1:d0a6d85072b02c02697bc60f2115756aa1bf89d8
Add some additional registers.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>