linux/drivers/gpu/drm/amd/include/asic_reg/gc, branch masterMirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=master2026-01-05T22:00:01Zdrm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to 10.3 (v2)2026-01-05T22:00:01ZTom St Denistom.stdenis@amd.com2025-12-02T15:05:51Zurn:sha1:5e213a985d103ecd348ed4e9ae71292d86be9a71
v2: Added SPI bits to sh_mask header
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: RLC-G VF Register Access Interface2026-01-05T21:59:57ZBokun Zhangbokun.zhang@amd.com2025-10-27T13:45:33Zurn:sha1:0dd72af5528a404fca78ef0cad26582d34560c9b
- Implement Gfx v12.1 VFi interface under SRIOV
- Redirect all RLCG interface access to new function after
Gfx v12.1
v2: squash in register updates
Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add gc v12_1_0 ip headers v42025-12-08T18:56:35ZHawking ZhangHawking.Zhang@amd.com2025-08-29T05:39:11Zurn:sha1:91c93c090dfc58a3dcc97bb5e43b27892e043e9f
Add header files for gc v12_1_0 register offsets
and shift masks
v2: Update gc v12_1_0 ip headers
v3: Update gc v12_1_0 ip headers
v4, v5: Clean up registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: Add support for more per-process flag2025-03-07T20:33:49ZHarish KasiviswanathanHarish.Kasiviswanathan@amd.com2025-01-14T21:02:21Zurn:sha1:cf6d949a409e09539477d32dbe7c954e4852e744
Add support for more per-process flags starting with option to configure
MFMA precision for gfx 9.5
v2: Change flag name to KFD_PROC_FLAG_MFMA_HIGH_PRECISION
Remove unused else condition
v3: Bump the KFD API version
v4: Missed SH_MEM_CONFIG__PRECISION_MODE__SHIFT define. Added it.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing GC 11.5.0 register2025-03-07T20:33:48ZTom St Denistom.stdenis@amd.com2025-03-06T17:31:56Zurn:sha1:0d1a686b542aaabfcfd254bc7711624d4ec20df0
Adds register needed for debugging purposes.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update gc_12_0_0 headers2024-06-05T15:03:10ZAlex Deucheralexander.deucher@amd.com2024-05-31T15:57:00Zurn:sha1:b592d01df6efa2a4a93e360358b1f45057c80dda
Add some additional registers.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h2024-05-23T19:13:34ZSunil Khatrisunil.khatri@amd.com2024-05-21T13:43:44Zurn:sha1:eb14b8f50516b543b3483a14b1f30001940e6305
IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR
Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add gc v12_0_0 ip headers (v4)2024-04-30T13:46:29ZHawking ZhangHawking.Zhang@amd.com2023-07-04T14:43:43Zurn:sha1:db4f0d544edf941941a96a2dd92ef65a418b6b73
v1: Add gc v12_0_0 register offset and shift masks
header files. (Hawking)
v2: Update gc v12_0_0 register offset and shift masks
header files to LSD version. (Likun)
v3: Update gc v12_0_0 register offset and shift masks
header files to RE3 version. (Likun)
v4: Updates (Alex)
v5: updates (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add support of gfx10 register dump2024-04-26T21:22:39ZSunil Khatrisunil.khatri@amd.com2024-04-16T10:44:12Zurn:sha1:c395dbb68b294d1de9a5ac6c9faaf8ac081123c3
Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add new bit definitions for GC 9.0 PROTECTION_FAULT_STATUS2024-03-20T17:37:36ZTao Zhoutao.zhou1@amd.com2024-02-19T07:29:51Zurn:sha1:b7b23877a2479951578dcaa8523314ed2cceccc3
Add UCE and FED bit definitions.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>