linux/drivers/gpu/drm/amd/include/asic_reg/uvd, branch masterMirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=master2024-08-13T14:26:48Zdrm/amdgpu/uvd4: fix mask and shift definitions2024-08-13T14:26:48ZRemington Brasgarbrasga@uci.edu2024-07-31T05:54:51Zurn:sha1:3834ce360067b4ee98fdef14571923500a0499a4
A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.
Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add mmUVD_FW_STATUS register to uvd7002020-09-17T21:59:54ZTom St Denistom.stdenis@amd.com2020-09-16T16:17:04Zurn:sha1:b6c91dadaffee8bf253b0b5ac26a2638c388c6c6
This register was requested for umr debugging support.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm amdgpu: SI UVD registers2020-07-01T05:59:24ZSonny Jiangsonny.jiang@amd.com2020-06-10T20:02:21Zurn:sha1:2282b4186dee80c89906d0ee10295393582c3afd
Add SI UVD registers files.
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include:cleanup vega10 uvd header files.2017-12-06T17:48:19ZFeifei XuFeifei.Xu@amd.com2017-11-23T03:09:07Zurn:sha1:5d735f83c2b06ba51f2fae6404da576c6847cb64
Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add uvd enc registers in header2017-10-06T21:43:53ZJames ZhuJames.Zhu@amd.com2017-10-02T00:00:07Zurn:sha1:d0e62855fa7aea4736297abcbe4f0777f1332883
Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Introduction of SI registers (v2)2016-11-11T15:21:07ZTom St Denistom.stdenis@amd.com2016-10-26T15:58:25Zurn:sha1:de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33
This introduces the SI registers in the amdgpu
driver style.
v2: squash duplicates fix
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: switch UVD code to use UVD_NO_OP for padding2016-08-24T20:25:05ZAlex Deucheralexander.deucher@amd.com2016-08-23T13:12:21Zurn:sha1:c8b4f288f4276078f169a404e2d1ac1535f82b93
Replace packet2's with packet0 writes to UVD_NO_OP. The
value written to UVD_NO_OP does not matter.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add support for UVD_NO_OP register2016-08-24T20:25:04ZAlex Deucheralexander.deucher@amd.com2016-08-22T21:58:14Zurn:sha1:8dd31d74acc1371d143fd0b2795dc3d16fb47202
Writes to this register are the preferred way to do NOPs.
Bump the driver version as well.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: implement UVD VM mode for Stoney v22016-07-29T18:36:57ZChristian Königchristian.koenig@amd.com2016-06-23T10:11:46Zurn:sha1:0f30a397d9824cc81722d9912ae6ec9cec2b929b
Starting with Stoney we support running UVD in VM mode as well.
v2: rebased, only enable on Polaris for now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: handle more than 10 UVD sessions (v2)2016-05-05T00:20:23ZArindam Natharindam.nath@amd.com2016-04-12T11:46:15Zurn:sha1:c036554170fcc2238c32a7edd72c1b61b886428a
Change History
--------------
v2:
- Make firmware version check correctly. Firmware
versions >= 1.80 should all support 40 UVD
instances.
- Replace AMDGPU_MAX_UVD_HANDLES with max_handles
variable.
v1:
- The firmware can handle upto 40 UVD sessions.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>