linux/drivers/gpu/drm/amd/include/asic_reg, branch master

drm/amd/display: Update underflow detection for DCN42

2026-03-23T18:13:32Z

[Why] The DCN42 underflow detection functions in dcn42_optc.c use OPTC_RSMU_UNDERFLOW register but the register offset definitions were missing from dcn_4_2_0_offset.h and dcn42_resource.h. [How] Add missing register definitions. Fixes: e56e3cff2a1b ("drm/amd/display: Sync dcn42 with DC 3.2.373") Reviewed-by: Alex Hung Signed-off-by: Roman Li Signed-off-by: Chuanyu Tseng Signed-off-by: Alex Deucher

drm/amdgpu: Add lsdma v7_1_0 ip headers

2026-03-11T17:58:07Z

Add header files for lsdma v7_1_0 register offsets and shift masks Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amd/display: Sync dcn42 with DC 3.2.373

2026-03-11T17:58:07Z

This patch provides a bulk merge to align driver support for DCN42 with Display Core version 3.2.373. It includes upgrade for: - clk_mgr - dml2/dml21 - optc - hubp - mpc - optc - hwseq Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Enable dcn42 DC clk_mgr

2026-03-11T17:58:06Z

Add support for DCN 4.2 clock manager. Acked-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox

2026-03-04T16:50:56Z

The reason the RAP is not granting access to 0x58200 is that a dedicated RSMU slot would have to be spent for this address range, and MPASP is close to running out of RSMU slots. This will help to fix PSP TOC load failure during secureboot. GFX Driver Need to use indirect access for SMN address regs. Signed-off-by: sguttula Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amd/display: Add dcn42 register headers

2026-02-23T19:28:32Z

Register headers for the following IPs: - DCN 4.2.0 - DPCS 4.0.0 Signed-off-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amdgpu: Add THM 15.0.0 headers

2026-01-08T16:41:30Z

Add headers for THM 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher

drm/amdgpu: add SMUIO 15.0.0 headers

2026-01-08T16:41:25Z

Add headers for SMUIO 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher

drm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to 10.3 (v2)

2026-01-05T22:00:01Z

v2: Added SPI bits to sh_mask header Signed-off-by: Tom St Denis Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: RLC-G VF Register Access Interface

2026-01-05T21:59:57Z

- Implement Gfx v12.1 VFi interface under SRIOV - Redirect all RLCG interface access to new function after Gfx v12.1 v2: squash in register updates Signed-off-by: Bokun Zhang Signed-off-by: Alex Deucher