linux/drivers/gpu/drm/amd/include/asic_reg, branch v4.7

drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3D

2016-05-05T00:25:02Z

Signed-off-by: Flora Cui Reviewed-by: Jammy Zhou Signed-off-by: Alex Deucher

drm/amd: add DCE 11.2 register headers

2016-05-05T00:23:19Z

Add register headers for DCE (Display and Composition Engine) 11.2. Reviewed-by: Ken Wang Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: handle more than 10 UVD sessions (v2)

2016-05-05T00:20:23Z

Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath Signed-off-by: Ayyappa Chandolu Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/gfx7: add MTYPE definition

2016-03-17T17:15:43Z

Signed-off-by: Flora Cui Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher

drm/amd/include: Update dce 8 headers for dal

2016-02-12T20:31:47Z

Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher

drm/amd: add dce8 enum register header

2016-02-10T19:17:02Z

This adds the DCE8 enum header. Acked-by: Harry Wentland Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.h

2015-12-21T21:42:12Z

Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by new powerplay code for tonga and fiji. Reviewed-by: Alex Deucher Signed-off-by: yanyang1

drm/amd: add new gfx8 register definitions for EDC

2015-12-02T20:54:18Z

EDC is a RAS feature for on chip memory. Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: add GFX 8.1 register headers

2015-10-28T20:49:03Z

Minor differences compared to GFX 8.0 Signed-off-by: Alex Deucher

drm/amdgpu: Add Fiji smu 7.1.3 headers (v2)

2015-08-17T20:50:25Z

v2: agd5f: prepare for release Signed-off-by: David Zhang Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou Reviewed-by: Christian König