<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include/asic_reg, branch v4.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.9'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-09-19T18:38:24Z</updated>
<entry>
<title>drm/amdgpu: implement raster configuration for gfx v6</title>
<updated>2016-09-19T18:38:24Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2016-09-09T08:37:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=865ab832ba78a1baf03fed90dccf5088e63a3aa3'/>
<id>urn:sha1:865ab832ba78a1baf03fed90dccf5088e63a3aa3</id>
<content type='text'>
This patch is to implement the raster configuration and harvested
configuration of gfx v6.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Edward O'Callaghan &lt;funfunctor@folklore1984.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add si implementation v10</title>
<updated>2016-08-31T16:11:19Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:08:49Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=62a37553414a344491c64e8fd89577dcc1b8bcbb'/>
<id>urn:sha1:62a37553414a344491c64e8fd89577dcc1b8bcbb</id>
<content type='text'>
v5: rebase fixes
v6: add mgcg arrays
v7: rebase fixes
v8: rebase fixes
v9: add get_disabled_bios(), make get_xclk static
v10: fix oland and hainan asic specific handle at si_program_aspm

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add DMA implementation for si v8</title>
<updated>2016-08-31T16:10:51Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:05:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=30d1574fa4c71cf390ae4af57585a850612db8f7'/>
<id>urn:sha1:30d1574fa4c71cf390ae4af57585a850612db8f7</id>
<content type='text'>
v4: rebase fixes
v5: use the generic nop fill
v6: rebase fixes
v7: rebase fixes
    copy count fixes from Jonathan
    general cleanup
    add fill buffer implementation
v8: adapt write_pte and copy_pte to latest changes

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add display controller implementation for si v10</title>
<updated>2016-08-31T16:10:19Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T06:03:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e2cdf640cbb5b7d6643e1c8ad54bf3bfc99d4d48'/>
<id>urn:sha1:e2cdf640cbb5b7d6643e1c8ad54bf3bfc99d4d48</id>
<content type='text'>
v4: rebase fixups
v5: more fixes based on dce8 code
v6: squash in dmif offset fix
v7: rebase fixups
v8: rebase fixups, drop some debugging remnants
v9: fix BE build
v10: include Marek's tiling fixes, add support for
     page_flip_target, set MASTER_UDPATE_MODE=0,
     fix cursor

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add si header files v4</title>
<updated>2016-08-31T16:09:08Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-01-19T05:53:10Z</published>
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<id>urn:sha1:0f27e46258ee73e2fd149f91cb176475ce9b7537</id>
<content type='text'>
v4: drop unused DCE6 macro

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch UVD code to use UVD_NO_OP for padding</title>
<updated>2016-08-24T20:25:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-23T13:12:21Z</published>
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<id>urn:sha1:c8b4f288f4276078f169a404e2d1ac1535f82b93</id>
<content type='text'>
Replace packet2's with packet0 writes to UVD_NO_OP.  The
value written to UVD_NO_OP does not matter.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add support for UVD_NO_OP register</title>
<updated>2016-08-24T20:25:04Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2016-08-22T21:58:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8dd31d74acc1371d143fd0b2795dc3d16fb47202'/>
<id>urn:sha1:8dd31d74acc1371d143fd0b2795dc3d16fb47202</id>
<content type='text'>
Writes to this register are the preferred way to do NOPs.

Bump the driver version as well.

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new definition in bif header</title>
<updated>2016-07-29T18:37:11Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2016-07-14T16:31:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e595d7f03b48f5f311c9289c070a2a14636ad362'/>
<id>urn:sha1:e595d7f03b48f5f311c9289c070a2a14636ad362</id>
<content type='text'>
This patch adds new definition in bif header, and will be used on
iceland HW powertune part.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement UVD VM mode for Stoney v2</title>
<updated>2016-07-29T18:36:57Z</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-06-23T10:11:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0f30a397d9824cc81722d9912ae6ec9cec2b929b'/>
<id>urn:sha1:0f30a397d9824cc81722d9912ae6ec9cec2b929b</id>
<content type='text'>
Starting with Stoney we support running UVD in VM mode as well.

v2: rebased, only enable on Polaris for now.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add shared definitions for di/dt feature.</title>
<updated>2016-07-07T19:06:22Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-06-08T04:52:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9a88d22bb090f39e234bec9e4d416c8acdcdbb93'/>
<id>urn:sha1:9a88d22bb090f39e234bec9e4d416c8acdcdbb93</id>
<content type='text'>
v1: delete some comflict definitions between polaris and fiji.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
