linux/drivers/gpu/drm/amd/include/asic_reg, branch v6.3Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v6.32023-01-17T21:11:52Zdrm/amdgpu: correct query xgmi3x16 pcs error status2023-01-17T21:11:52ZStanley.YangStanley.Yang@amd.com2023-01-16T07:42:36Zurn:sha1:442d61af795c1441614064d8e6f2309223a8b342
There is xgmi3x16 pcs error status for aldebaran, driver should
check xgmi3x16 pcs error status field instead of gopx16 pcs error
status field.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers2023-01-17T21:11:50ZYiPeng ChaiYiPeng.Chai@amd.com2023-01-05T06:52:51Zurn:sha1:79d949a2d688b09b1ff840a2366a8cfe1b7a2651
V2:
Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register
offset and shift masks.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add df v4_3 headers2022-12-15T17:19:22ZCandice Licandice.li@amd.com2022-09-19T06:44:40Zurn:sha1:6c03a3fc912f74fe2ff588b42d30f52bc9001ab8
Add df v4_3 header files.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add missing license to some files2022-11-23T15:31:31ZAlex Deucheralexander.deucher@amd.com2022-11-21T17:17:33Zurn:sha1:e93e075d340859af772214c267d27f09f9db3e51
The driver is MIT, so add the licenses.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2265
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add register definition for VCN RAS initialization2022-11-23T15:31:31ZTao Zhoutao.zhou1@amd.com2022-10-27T09:50:56Zurn:sha1:88733d68014f06d4aae8ef0673ee31602ef1f0a7
Prepare for enableing VCN RAS poison.
v2: move SHIFT and MASK definitions to related sh_mask.h file.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Update umc v8_10_0 headers2022-10-11T15:05:35ZCandice Licandice.li@amd.com2022-09-26T08:18:56Zurn:sha1:6dddc1eb9632b0eb6098d1dc849e8acb2408c1b6
Add GeccCtrl offset and mask to umc v8_10_0 headers.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.12022-09-29T13:41:43ZTom St Denistom.stdenis@amd.com2022-09-23T12:55:50Zurn:sha1:82806c25d5e9d927ecb68c0c3679dd41187c9af6
These are used by umr to sort the hive nodes since the kernel
initializes the nodes in order of bus enumeration not XGMI hive
enumeration.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: update GC 10.3.0 pwrdec2022-09-13T16:54:23ZTom St Denistom.stdenis@amd.com2022-09-08T13:36:18Zurn:sha1:1ed1f6be6eb3daa8097d6419dde516c9854a8790
The 10.3 GC headers were missing most of the pwrdec block.
This patch adds the registers and bits present in the 10.1 header
but based on the contents of the 10.3 specs.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers2022-09-08T02:28:42ZTom St Denistom.stdenis@amd.com2022-09-07T14:18:01Zurn:sha1:780244a2fe8a82424c85f4cb15e45d0bbeec8f26
The TCC_DISABLE registers were not included in the 10.3 headers and
instead just placed directly in the gfx_v10_0.c source. This patch
adds them to the headers so tools like umr can scan them and support them.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add gc v11_0_3 ip headers2022-08-30T20:36:42ZFrank MinFrank.Min@amd.com2022-06-27T03:05:43Zurn:sha1:a40a92af46113e200b9110c4040a465771d28b35
Add gc v11_0_3 register offset and shift masks
header files
v2: update registers (Alex)
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>