<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include/kgd_pp_interface.h, branch v5.10</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.10</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.10'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-09-29T20:12:16Z</updated>
<entry>
<title>drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU.</title>
<updated>2020-09-29T20:12:16Z</updated>
<author>
<name>Xiaojian Du</name>
<email>Xiaojian.Du@amd.com</email>
</author>
<published>2020-09-27T09:07:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=12a6727dee5d1119fc1556b870848f511414bf5d'/>
<id>urn:sha1:12a6727dee5d1119fc1556b870848f511414bf5d</id>
<content type='text'>
This patch is to add one sysfs file -- "pp_od_clk_voltage" for
Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10.
This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can
be used to configure the min value and the max value for gfx clock limited in the
safe range.

Command guide:
echo "s level clock" &gt; pp_od_clk_voltage
	s - adjust teh sclk level
	level - 0 or 1, "0" represents the min value, "1" represents the max value
	clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the
                OD_RANGE limits.
Example:
$ cat pp_od_clk_voltage
OD_SCLK:
0:        200Mhz
1:       1400Mhz
OD_RANGE:
SCLK:     200MHz       1400MHz

$ echo "s 0 600" &gt; pp_od_clk_voltage
$ echo "s 1 1000" &gt; pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0:        600Mhz
1:       1000Mhz
OD_RANGE:
SCLK:     200MHz       1400MHz

Signed-off-by: Xiaojian Du &lt;Xiaojian.Du@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)</title>
<updated>2020-08-06T19:43:56Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-07-23T10:03:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=25c933b1c4fcfaa65ed735e9782fdb2622f7b7e8'/>
<id>urn:sha1:25c933b1c4fcfaa65ed735e9782fdb2622f7b7e8</id>
<content type='text'>
A new interface for UMD to retrieve gpu metrics data.

V2: rich the documentation

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: define an universal data structure for gpu metrics (V4)</title>
<updated>2020-08-06T19:43:37Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-07-23T08:07:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=39c5a1cef84b4bc70123400d75f0fe637e1df6a6'/>
<id>urn:sha1:39c5a1cef84b4bc70123400d75f0fe637e1df6a6</id>
<content type='text'>
Thus we can provide an interface for UMD to retrieve gpu metrics data.

V2: better naming and comments
V3: two structures created for dGPU and APU separately
V4: add driver attached timestamp

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2</title>
<updated>2019-11-06T21:27:46Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-10-31T01:41:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3e454860f2a469e82c0f0dd7ff058a70a84a6f8b'/>
<id>urn:sha1:3e454860f2a469e82c0f0dd7ff058a70a84a6f8b</id>
<content type='text'>
Add xgmi pstate setting on powerplay routine.

V2: split the change of is_support_sw_smu_xgmi into a separate patch

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: enable df cstate control on powerplay routine</title>
<updated>2019-10-15T19:48:09Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-10-10T03:34:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=06615f9a0c0d68566fc069729aade64a7dbadd58'/>
<id>urn:sha1:06615f9a0c0d68566fc069729aade64a7dbadd58</id>
<content type='text'>
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: Add interface to lock SMU HW I2C.</title>
<updated>2019-08-27T13:17:42Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-05-01T22:19:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9'/>
<id>urn:sha1:6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9</id>
<content type='text'>
v2:
PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
over I2C bus and engine disable thermal control access to
force SMU stop using the I2C bus until the issue is reslolved.

Expose and call vega20_is_smc_ram_running to skip locking when SMU
FW is not yet loaded.

v3:
Remove the prevoius hack as the SMU found the bug.

v5: Typo fix

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/poweplay: Add amd_pm_funcs callback for mode 2</title>
<updated>2019-08-15T16:00:30Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-08-14T20:26:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e97204ead61c79c292761c5c934a02dfe9967b71'/>
<id>urn:sha1:e97204ead61c79c292761c5c934a02dfe9967b71</id>
<content type='text'>
Add callback to call the new mode2 reset interface.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add new sensor type for VCN powergate status</title>
<updated>2019-07-31T04:48:34Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-07-22T01:51:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9829e3d89b6ea9027542d094cdb8a434eef4b3aa'/>
<id>urn:sha1:9829e3d89b6ea9027542d094cdb8a434eef4b3aa</id>
<content type='text'>
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/powerplay: add a new interface to set the mp1 state</title>
<updated>2019-07-31T04:24:21Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-07-25T14:41:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a2c28e34f8c42e35f5f2990d558d367152e63c27'/>
<id>urn:sha1:a2c28e34f8c42e35f5f2990d558d367152e63c27</id>
<content type='text'>
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: correct SW SMU valid mapping check</title>
<updated>2019-07-18T19:18:07Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-07-11T02:23:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7e01a2ec96bf8a149c5e83d0352cf6ea286275cf'/>
<id>urn:sha1:7e01a2ec96bf8a149c5e83d0352cf6ea286275cf</id>
<content type='text'>
Current implementation is not actually able to detect
invalid message/table/workload mapping.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
