linux/drivers/gpu/drm/amd/include/kgd_pp_interface.h, branch v5.12

drm/amd/pm: implement processor fine grain feature for vangogh (v3)

2021-01-14T04:52:58Z

This patch is to implement the processor fine grain feature for vangogh. It's similar with gfx clock, the only difference is below: echo "p core_id level value" > pp_od_clk_voltage 1. "p" - set the cclk (processor) frequency 2. "core_id" - 0/1/2/3, represents which cpu core you want to select 2. "level" - 0 or 1, "0" represents the min value, "1" represents the max value 3. "value" - the target value of cclk frequency, it should be limited in the safe range v2: fix some missing changes as Evan's suggestion. v3: add version check and fix the restore. Signed-off-by: Huang Rui Reviewed-by: Evan Quan Signed-off-by: Alex Deucher

drm/amd/pm: implement the processor clocks which read by metric

2021-01-14T04:52:51Z

The core processor clocks will be stored in smu metric table, then we add this runtime information into amdgpu_pm_info interface. Signed-off-by: Huang Rui Reviewed-by: Evan Quan Signed-off-by: Alex Deucher

drm/amd/pm: support overdrive vddgfx offset setting(V2)

2020-12-23T20:07:03Z

This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. For these ASICs, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset". V2: limit the smu_version check for Sienna Cichlid only Here are some sample usages about this new OD setting: 1. Check current vddgfx offset setting by cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 0mV ... ... 2. Set new vddgfx offset by echo "vo 10" > /sys/class/drm/card0/device/pp_od_clk_voltage cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 10mV ... ... 3. Commit the new setting by echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry (v2)

2020-11-13T22:29:45Z

The new amdgpu_gfx_state_change_set() funtion can support set GFX power change status to D0/D3. v2: squash in warning fix (Alex) Signed-off-by: Prike Liang Acked-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU.

2020-09-29T20:12:16Z

This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du Reviewed-by: Kevin Wang Reviewed-by: Huang Rui Signed-off-by: Alex Deucher

drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)

2020-08-06T19:43:56Z

A new interface for UMD to retrieve gpu metrics data. V2: rich the documentation Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/powerplay: define an universal data structure for gpu metrics (V4)

2020-08-06T19:43:37Z

Thus we can provide an interface for UMD to retrieve gpu metrics data. V2: better naming and comments V3: two structures created for dGPU and APU separately V4: add driver attached timestamp Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2

2019-11-06T21:27:46Z

Add xgmi pstate setting on powerplay routine. V2: split the change of is_support_sw_smu_xgmi into a separate patch Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/powerplay: enable df cstate control on powerplay routine

2019-10-15T19:48:09Z

Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher

drm/amd/powerplay: Add interface to lock SMU HW I2C.

2019-08-27T13:17:42Z

v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the prevoius hack as the SMU found the bug. v5: Typo fix Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher