<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include/kgd_pp_interface.h, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-08-27T13:17:42Z</updated>
<entry>
<title>drm/amd/powerplay: Add interface to lock SMU HW I2C.</title>
<updated>2019-08-27T13:17:42Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-05-01T22:19:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9'/>
<id>urn:sha1:6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9</id>
<content type='text'>
v2:
PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
over I2C bus and engine disable thermal control access to
force SMU stop using the I2C bus until the issue is reslolved.

Expose and call vega20_is_smc_ram_running to skip locking when SMU
FW is not yet loaded.

v3:
Remove the prevoius hack as the SMU found the bug.

v5: Typo fix

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/poweplay: Add amd_pm_funcs callback for mode 2</title>
<updated>2019-08-15T16:00:30Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-08-14T20:26:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e97204ead61c79c292761c5c934a02dfe9967b71'/>
<id>urn:sha1:e97204ead61c79c292761c5c934a02dfe9967b71</id>
<content type='text'>
Add callback to call the new mode2 reset interface.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add new sensor type for VCN powergate status</title>
<updated>2019-07-31T04:48:34Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-07-22T01:51:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9829e3d89b6ea9027542d094cdb8a434eef4b3aa'/>
<id>urn:sha1:9829e3d89b6ea9027542d094cdb8a434eef4b3aa</id>
<content type='text'>
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/powerplay: add a new interface to set the mp1 state</title>
<updated>2019-07-31T04:24:21Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-07-25T14:41:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a2c28e34f8c42e35f5f2990d558d367152e63c27'/>
<id>urn:sha1:a2c28e34f8c42e35f5f2990d558d367152e63c27</id>
<content type='text'>
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: correct SW SMU valid mapping check</title>
<updated>2019-07-18T19:18:07Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-07-11T02:23:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7e01a2ec96bf8a149c5e83d0352cf6ea286275cf'/>
<id>urn:sha1:7e01a2ec96bf8a149c5e83d0352cf6ea286275cf</id>
<content type='text'>
Current implementation is not actually able to detect
invalid message/table/workload mapping.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: expose Vega20 realtime memory utilization</title>
<updated>2019-05-24T17:20:48Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-04-19T05:54:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1846e3f9e76ceaac86072eb897393ee24d1d870e'/>
<id>urn:sha1:1846e3f9e76ceaac86072eb897393ee24d1d870e</id>
<content type='text'>
Enable realtime memory utilization report on Vega20.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: support hwmon temperature channel labels V2</title>
<updated>2019-05-24T17:20:47Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-04-17T07:45:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2adc11564c42b63827eaf1cf9d61da2f79b9c978'/>
<id>urn:sha1:2adc11564c42b63827eaf1cf9d61da2f79b9c978</id>
<content type='text'>
Expose temp[1-3]_label hwmon interfaces. While temp2_label
and temp3_label are visible for SOC15 dGPUs only.

- V2: correct temp1_label as "edge"

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: expose current hotspot and memory temperatures V2</title>
<updated>2019-05-24T17:20:47Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-04-18T05:51:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a34d1166b47c8497cffda4da7c14182cb3420362'/>
<id>urn:sha1:a34d1166b47c8497cffda4da7c14182cb3420362</id>
<content type='text'>
Two new hwmon interfaces(temp2_input and temp3_input) are added.
They are supported on SOC15 dGPUs only.

- V2: correct thermal sensor output

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: support retrieving and adjusting dcefclock power levels V2</title>
<updated>2019-01-25T21:15:34Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-01-14T09:37:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d7e28e2d6b518af760c81ba578ecf4e4b0c0f401'/>
<id>urn:sha1:d7e28e2d6b518af760c81ba578ecf4e4b0c0f401</id>
<content type='text'>
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power
levels.

V2: expose this interface for Vega10 and later ASICs only

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: support retrieving and adjusting fclock power levels V2</title>
<updated>2019-01-25T21:15:34Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-01-14T07:44:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=828e37efe802ba8c868922af23099638fde5b7b4'/>
<id>urn:sha1:828e37efe802ba8c868922af23099638fde5b7b4</id>
<content type='text'>
User can use "pp_dpm_fclk" to retrieve and adjust fclock power
levels.

V2: expose this interface for Vega20 and later ASICs only

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
