<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include, branch v5.14</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.14</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.14'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-08-06T15:33:50Z</updated>
<entry>
<title>drm/amdgpu: set RAS EEPROM address from VBIOS</title>
<updated>2021-08-06T15:33:50Z</updated>
<author>
<name>John Clements</name>
<email>john.clements@amd.com</email>
</author>
<published>2021-08-04T09:11:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=39932ef75897bfcb8ba1120e7b09d615d74762fd'/>
<id>urn:sha1:39932ef75897bfcb8ba1120e7b09d615d74762fd</id>
<content type='text'>
update to latest atombios fw table

[Backport to 5.14 - Alex]

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1670
Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;.
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/pm: drop smu_v13_0_1.c|h files for yellow carp</title>
<updated>2021-07-13T15:48:11Z</updated>
<author>
<name>Xiaomeng Hou</name>
<email>Xiaomeng.Hou@amd.com</email>
</author>
<published>2021-07-01T06:09:18Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=21cf0293d500f198ad886cbdcd3ff65f82b35edf'/>
<id>urn:sha1:21cf0293d500f198ad886cbdcd3ff65f82b35edf</id>
<content type='text'>
Since there's nothing special in smu implementation for yellow carp,
it's better to reuse the common smu_v13_0 interfaces and drop the
specific smu_v13_0_1.c|h files.

v2: remove the duplicate register offset and shift mask header files as
well.

Signed-off-by: Xiaomeng Hou &lt;Xiaomeng.Hou@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update NV SIMD-per-CU to 2</title>
<updated>2021-07-01T04:05:18Z</updated>
<author>
<name>Joseph Greathouse</name>
<email>Joseph.Greathouse@amd.com</email>
</author>
<published>2021-06-30T02:08:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=aa6158112645aae514982ad8d56df64428fcf203'/>
<id>urn:sha1:aa6158112645aae514982ad8d56df64428fcf203</id>
<content type='text'>
Navi series GPUs have 2 SIMDs per CU (and then 2 CUs per WGP).
The NV enum headers incorrectly listed this as 4, which later meant
we were incorrectly reporting the number of SIMDs in the HSA
topology. This could cause problems down the line for user-space
applications that want to launch a fixed amount of work to each
SIMD.

Signed-off-by: Joseph Greathouse &lt;Joseph.Greathouse@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Enabling eDP no power sequencing with DAL feature mask</title>
<updated>2021-06-30T03:41:22Z</updated>
<author>
<name>Zhan Liu</name>
<email>zhan.liu@amd.com</email>
</author>
<published>2021-06-14T18:54:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a51482458dafb836dbf7c8ae3200ca8db7348201'/>
<id>urn:sha1:a51482458dafb836dbf7c8ae3200ca8db7348201</id>
<content type='text'>
[Why]
Sometimes, DP receiver chip power-controlled externally by an
Embedded Controller could be treated and used as eDP,
if it drives mobile display. In this case,
we shouldn't be doing power-sequencing, hence we can skip
waiting for T7-ready and T9-ready."

[How]
Added a feature mask to enable eDP no power sequencing feature.

To enable this, set 0x10 flag in amdgpu.dcfeaturemask on
Linux command line.

Signed-off-by: Zhan Liu &lt;zhan.liu@amd.com&gt;
Reviewed-by: Nikola Cornij &lt;Nikola.Cornij@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add interface to get Calibrated Avg Level from FIFO</title>
<updated>2021-06-15T21:25:41Z</updated>
<author>
<name>Wesley Chalmers</name>
<email>Wesley.Chalmers@amd.com</email>
</author>
<published>2021-05-06T17:22:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a659f2fdf8b9b186c9324e05baa9e2835d47c7d2'/>
<id>urn:sha1:a659f2fdf8b9b186c9324e05baa9e2835d47c7d2</id>
<content type='text'>
[WHY]
Hardware has handed down a new sequence requiring the value of this
register be read from clk_mgr.

Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Anson Jacob &lt;Anson.Jacob@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Add u64 throttler status field to gpu_metrics</title>
<updated>2021-06-10T15:44:25Z</updated>
<author>
<name>Graham Sider</name>
<email>Graham.Sider@amd.com</email>
</author>
<published>2021-06-03T14:49:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=22a7dcf58059f6d89fb7e2393c0ddc48c7d06266'/>
<id>urn:sha1:22a7dcf58059f6d89fb7e2393c0ddc48c7d06266</id>
<content type='text'>
This patch set adds support for a new ASIC independant u64 throttler
status field (indep_throttle_status). Piggybacks off the
gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to
v2_2) to add field.

Signed-off-by: Graham Sider &lt;Graham.Sider@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/pm: add kernel documentation for smu_get_power_limit</title>
<updated>2021-06-08T16:14:11Z</updated>
<author>
<name>Darren Powell</name>
<email>darren.powell@amd.com</email>
</author>
<published>2021-05-27T03:27:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=90a681c5e43e86fb4b16a3c4b9aa2c2d680f5168'/>
<id>urn:sha1:90a681c5e43e86fb4b16a3c4b9aa2c2d680f5168</id>
<content type='text'>
 added doc tag "amdgpu_pp_power" with description
 added tags for enums  pp_power_limit_level, pp_power_type
 added tag for function smu_get_power_limit

Test:
* Temporary insertion into Documentation/gpu/amdgpu.rst
------------START------------
Power Limit
-----------
.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
   :doc: amdgpu_pp_power

.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
   :identifiers: pp_power_limit_level

.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
   :identifiers: pp_power_type

.. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
   :identifiers: smu_get_power_limit
-------------END-------------

Signed-off-by: Darren Powell &lt;darren.powell@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/pm: modify Powerplay API get_power_limit to use new pp_power enums</title>
<updated>2021-06-08T16:13:49Z</updated>
<author>
<name>Darren Powell</name>
<email>darren.powell@amd.com</email>
</author>
<published>2021-05-22T04:13:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=04bec52127b131b828e0305e02366e64969c5efc'/>
<id>urn:sha1:04bec52127b131b828e0305e02366e64969c5efc</id>
<content type='text'>
 updated {amd_pm_funcs}-&gt;get_power_limit() signature
 rewrote pp_get_power_limit to use new enums
 pp_get_power_limit now returns -EOPNOTSUPP for unknown power limit
 update calls to {amd_pm_funcs}-&gt;get_power_limit()

* Test Notes
* testing hardware was NAVI10 (tests SMU path)
** needs testing on VANGOGH
** needs testing on SMU &lt; 11
** ie, one of
 TOPAZ, FIJI, TONGA, POLARIS10, POLARIS11, POLARIS12, VEGAM, CARRIZO,
 STONEY, VEGA10, VEGA12,VEGA20, RAVEN, BONAIRE, HAWAII

* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

Signed-off-by: Darren Powell &lt;darren.powell@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/pm: clean up smu_get_power_limit function signature</title>
<updated>2021-06-08T16:13:40Z</updated>
<author>
<name>Darren Powell</name>
<email>darren.powell@amd.com</email>
</author>
<published>2021-05-22T02:37:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a40a020de27401828692e94e717777bd7112452e'/>
<id>urn:sha1:a40a020de27401828692e94e717777bd7112452e</id>
<content type='text'>
 add two new powerplay enums (limit_level, type)
 add enums to smu_get_power_limit signature
 remove input bitfield stuffing of output variable limit
 update calls to smu_get_power_limit

* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

Signed-off-by: Darren Powell &lt;darren.powell@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update atomfirmware for DCN3.1 phy tuning and eDP caps</title>
<updated>2021-06-04T20:03:25Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-05-19T14:38:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=753625643e218eb72a6e7b7df87db595a446931a'/>
<id>urn:sha1:753625643e218eb72a6e7b7df87db595a446931a</id>
<content type='text'>
[Why &amp; How]
We'll need these in driver for phy tuning in DCN3.1.

Multiple eDP support also requires understanding which LCD the backlight
curve in atombios is for.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
