<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-09-17T19:22:29Z</updated>
<entry>
<title>drm/amd/display: update renoir_ip_offset.h</title>
<updated>2019-09-17T19:22:29Z</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2019-09-04T05:21:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f79e06bd44e5be98b75f71ac0cde6c16be278180'/>
<id>urn:sha1:f79e06bd44e5be98b75f71ac0cde6c16be278180</id>
<content type='text'>
This patch updates MP1_BASE in renoir_ip_offset.h

Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header for VG/RV series</title>
<updated>2019-08-30T20:37:17Z</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2018-12-14T03:16:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=75966255881127f4a2c0ab7e18d9224672bdeddb'/>
<id>urn:sha1:75966255881127f4a2c0ab7e18d9224672bdeddb</id>
<content type='text'>
In Renoir's emulator, those chicken bits need to be programmed.

Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add Renoir registers (v3)</title>
<updated>2019-08-29T20:52:32Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2019-07-25T19:51:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b593bce59bfa25d9abbf220b6614396ccd965b1b'/>
<id>urn:sha1:b593bce59bfa25d9abbf220b6614396ccd965b1b</id>
<content type='text'>
add registers for dcn, clk, and renoir ip offsets

v2: header cleanup (Alex)
v3: Add DPCS registers (Hersen)

Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: Add interface to lock SMU HW I2C.</title>
<updated>2019-08-27T13:17:42Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-05-01T22:19:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9'/>
<id>urn:sha1:6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9</id>
<content type='text'>
v2:
PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
over I2C bus and engine disable thermal control access to
force SMU stop using the I2C bus until the issue is reslolved.

Expose and call vega20_is_smc_ram_running to skip locking when SMU
FW is not yet loaded.

v3:
Remove the prevoius hack as the SMU found the bug.

v5: Typo fix

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Import smuio_11_0 headers for EEPROM access on Vega20</title>
<updated>2019-08-27T13:17:27Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-04-30T17:58:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6a3068065fa4d6f931a12573d4bda5d85261cee2'/>
<id>urn:sha1:6a3068065fa4d6f931a12573d4bda5d85261cee2</id>
<content type='text'>
v3: Merge CKSVII2C_IC regs into exsisting headers.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: add flag for multi-display mclk switching</title>
<updated>2019-08-23T16:33:00Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-08-22T19:17:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d99f38aed1a03f78cb7ae04d86e7fc5ac70411e3'/>
<id>urn:sha1:d99f38aed1a03f78cb7ae04d86e7fc5ac70411e3</id>
<content type='text'>
Add a dcfeaturemask flag for mclk switching.  Disable by default;
enable once the feature has seen more testing.

Set amdgpu.dcfeaturemask=2 on the kernel command line in grub
to enable this.

Acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'</title>
<updated>2019-08-22T03:16:55Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2019-08-18T15:59:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6a9d8de7e9c75334949c005f9b1c50c6f857606d'/>
<id>urn:sha1:6a9d8de7e9c75334949c005f9b1c50c6f857606d</id>
<content type='text'>
'_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use
'_navi12_ip_offset_HEADER' instead here.

Reviewed-by: Xiaojie Yuan &lt;xiaojie.yuan@amd.com&gt;
Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/poweplay: Add amd_pm_funcs callback for mode 2</title>
<updated>2019-08-15T16:00:30Z</updated>
<author>
<name>Andrey Grodzovsky</name>
<email>andrey.grodzovsky@amd.com</email>
</author>
<published>2019-08-14T20:26:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e97204ead61c79c292761c5c934a02dfe9967b71'/>
<id>urn:sha1:e97204ead61c79c292761c5c934a02dfe9967b71</id>
<content type='text'>
Add callback to call the new mode2 reset interface.

Signed-off-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: implement querying ras error count for mmhub</title>
<updated>2019-08-15T15:51:50Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-13T07:46:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d6e0cbb152b35833a26772c86b338d8297ce609d'/>
<id>urn:sha1:d6e0cbb152b35833a26772c86b338d8297ce609d</id>
<content type='text'>
get mmhub ea ras error count by accessing EDC_CNT register

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add renoir header files (v2)</title>
<updated>2019-08-12T17:47:49Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2018-10-25T11:49:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d8a46257c22906db38590eb7986c07770bee002c'/>
<id>urn:sha1:d8a46257c22906db38590eb7986c07770bee002c</id>
<content type='text'>
This patch add all renoir header files.

v2: clean up headers (Alex)

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
