<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include, branch v5.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-02-25T16:30:42Z</updated>
<entry>
<title>amdgpu/gmc_v9: save/restore sdpif regs during S3</title>
<updated>2020-02-25T16:30:42Z</updated>
<author>
<name>Shirish S</name>
<email>shirish.s@amd.com</email>
</author>
<published>2020-01-27T11:05:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a3ed353cf8015ba84a0407a5dc3ffee038166ab0'/>
<id>urn:sha1:a3ed353cf8015ba84a0407a5dc3ffee038166ab0</id>
<content type='text'>
fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Shirish S &lt;shirish.s@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus</title>
<updated>2020-01-30T22:15:27Z</updated>
<author>
<name>Joseph Greathouse</name>
<email>Joseph.Greathouse@amd.com</email>
</author>
<published>2020-01-27T22:08:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=18c6b74e7cfc9a599917d9e98f9835de8208e19a'/>
<id>urn:sha1:18c6b74e7cfc9a599917d9e98f9835de8208e19a</id>
<content type='text'>
In previous gfx9 parts, S_BARRIER shader instructions are implicitly
S_WAITCNT 0 instructions as well. This setting turns off that
mechanism in Arcturus and beyond. With this, shaders must follow the
ISA guide insofar as putting in explicit S_WAITCNT operations even
after an S_BARRIER.

v2: Fix patch title to list component

Signed-off-by: Joseph Greathouse &lt;Joseph.Greathouse@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add EDC counter registers of gc for Arcturus</title>
<updated>2020-01-22T21:36:22Z</updated>
<author>
<name>Dennis Li</name>
<email>Dennis.Li@amd.com</email>
</author>
<published>2020-01-16T04:30:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=19cf0dd4b9d2771015fc9d74ec1b0b9203cf8c5a'/>
<id>urn:sha1:19cf0dd4b9d2771015fc9d74ec1b0b9203cf8c5a</id>
<content type='text'>
add reg headers to gc includes

v2: remove unused registers and fields in this patch set

Signed-off-by: Dennis Li &lt;Dennis.Li@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update mmhub 9.4.1 header files for Acrturus</title>
<updated>2020-01-22T21:35:42Z</updated>
<author>
<name>Dennis Li</name>
<email>Dennis.Li@amd.com</email>
</author>
<published>2020-01-13T08:15:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f519cd13c23e8c884011295b205c1463babbf416'/>
<id>urn:sha1:f519cd13c23e8c884011295b205c1463babbf416</id>
<content type='text'>
Add mask &amp; shift definition of MAM_D(0~3)MEM for all mmhub
ranges.

Signed-off-by: Dennis Li &lt;Dennis.Li@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: added support to get mGPU DRAM base</title>
<updated>2020-01-22T21:34:07Z</updated>
<author>
<name>John Clements</name>
<email>john.clements@amd.com</email>
</author>
<published>2020-01-17T04:18:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a6c44d2538c469f412c3fded0de2290494d762d7'/>
<id>urn:sha1:a6c44d2538c469f412c3fded0de2290494d762d7</id>
<content type='text'>
resolves issue with RAS error injection in mGPU configuration

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: John Clements &lt;john.clements@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/include: Add OCSC registers</title>
<updated>2020-01-16T18:41:06Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2020-01-07T20:28:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d1dcb05f0e45f97061d5c1f921aa038f1ae92c7b'/>
<id>urn:sha1:d1dcb05f0e45f97061d5c1f921aa038f1ae92c7b</id>
<content type='text'>
Add registers for handling Post Gamma Color Blending (OCSC), which is
useful for conversion from RGB-&gt;YUV for HDMI.

Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: use kiq to load the mqd of hiq queue for gfx v9 (v6)</title>
<updated>2020-01-16T18:34:50Z</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2019-12-25T07:50:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=35cd89d5a658dc26687a7a6909d35fee19a6b173'/>
<id>urn:sha1:35cd89d5a658dc26687a7a6909d35fee19a6b173</id>
<content type='text'>
There is an issue that CP will check the HIQ queue to be configured and mapped
with KIQ ring, otherwise, it will be unable to read back the secure buffer while
the gfxoff is enabled even with trusted IP blocks.

v1 -&gt; v2:
- Fix to remove surplus set_resources packets.
- Fill the whole configuration in MQD.
- Change the author as Aaron because he addressed the key point of this issue.
- Add kiq ring lock.

v2 -&gt; v3:
- Free the lock while in error return case.
- Remove the programming only needed by the queue is unmapped.

v3 -&gt; v4:
- Remove doorbell programming because it's used for restarting queue.
- Remove CP scheduler programming because map_queue packet will handle this.

v4 -&gt; v5:
- Remove cp_hqd_active because mec ucode will enable it while use map_queues.
- Revise goto out_unlock.
- Correct the right doorbell offset for HIQ that kfd driver assigned in the
  packet.

v5 -&gt; v6:
- Merge Arcturus fix into this patch because it will get oops in Arcturus
  platform.

Reported-by: Lisa Saturday &lt;Lisa.Saturday@amd.com&gt;
Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-and-Tested-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: flush TLB functions removal from kfd2kgd interface</title>
<updated>2020-01-16T18:34:42Z</updated>
<author>
<name>Alex Sierra</name>
<email>alex.sierra@amd.com</email>
</author>
<published>2019-12-20T06:00:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d175e9acf658334a4a0559a30c39c368a38d9dcd'/>
<id>urn:sha1:d175e9acf658334a4a0559a30c39c368a38d9dcd</id>
<content type='text'>
[Why]
kfd2kgd interface will be deprecated. This removal only covers TLB
invalidation for now. They have been replaced in amdgpu_amdkfd API.

[How]
TLB invalidate functions removed from the different amdkfd_gfx_v*
versions.

Signed-off-by: Alex Sierra &lt;alex.sierra@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add defines for DF and TCP Hashing</title>
<updated>2020-01-14T15:18:41Z</updated>
<author>
<name>Joseph Greathouse</name>
<email>Joseph.Greathouse@amd.com</email>
</author>
<published>2020-01-09T23:07:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ae99fc35ceea9ae9c496987d113187464b33b2b8'/>
<id>urn:sha1:ae99fc35ceea9ae9c496987d113187464b33b2b8</id>
<content type='text'>
On Arcturus, we need TC channel hashing, which is set by the
driver, to match DF hashing, which is set by VBIOS. To match
these, we plan to query the DF information and then properly
set the TC configuration bits to match them.

This patch adds the required fields to register definitions
in preparation for a future patch which will use them.

Signed-off-by: Joseph Greathouse &lt;Joseph.Greathouse@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file (v2)</title>
<updated>2020-01-14T15:18:09Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2020-01-09T15:37:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=351d5ac55c72ee6f6ad018e2a756b5fe09fceed3'/>
<id>urn:sha1:351d5ac55c72ee6f6ad018e2a756b5fe09fceed3</id>
<content type='text'>
(v2): Fix preprocessor tag

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
