<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include, branch v5.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-03-10T19:54:34Z</updated>
<entry>
<title>drm/amdkfd: Consolidate duplicated bo alloc flags</title>
<updated>2020-03-10T19:54:34Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2020-03-04T17:38:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1d251d90080a2721e97550973ab5efe772bc56bf'/>
<id>urn:sha1:1d251d90080a2721e97550973ab5efe772bc56bf</id>
<content type='text'>
ALLOC_MEM_FLAGS_* used are the same as the KFD_IOC_ALLOC_MEM_FLAGS_*,
but they are interweavedly used in kernel driver, resulting in bad
readability. For example, KFD_IOC_ALLOC_MEM_FLAGS_COHERENT is not
referenced in kernel, and it functions implicitly in kernel through
ALLOC_MEM_FLAGS_COHERENT, causing unnecessary confusion.

Replace all occurrences of ALLOC_MEM_FLAGS_* with
KFD_IOC_ALLOC_MEM_FLAGS_* to solve the problem.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add wafl2 ip headers</title>
<updated>2020-03-06T19:31:21Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2020-02-21T10:59:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=15a1fbdcfb519c2bd291ed01c6c94e0b89537a77'/>
<id>urn:sha1:15a1fbdcfb519c2bd291ed01c6c94e0b89537a77</id>
<content type='text'>
add wafl2 smn address and shift mask definition header files

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add xgmi ip headers</title>
<updated>2020-03-06T19:31:00Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2020-02-21T10:49:11Z</published>
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<id>urn:sha1:86edee9725a5fda9ac8a9911759feb8b1a653eda</id>
<content type='text'>
add xgmi ip smn address and shift mask header files

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Make get_tile_config() generic</title>
<updated>2020-02-28T21:59:20Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2020-02-26T17:49:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fd7d08bad7a4f255330422a11c7da9a9b8683eff'/>
<id>urn:sha1:fd7d08bad7a4f255330422a11c7da9a9b8683eff</id>
<content type='text'>
Given we can query all the asic specific information from amdgpu_gfx_config,
we can make get_tile_config() generic.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Avoid ambiguity by indicating it's cp queue</title>
<updated>2020-02-26T19:20:05Z</updated>
<author>
<name>Yong Zhao</name>
<email>Yong.Zhao@amd.com</email>
</author>
<published>2020-01-30T23:35:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e6945304187deae0a28ebc65008ec11277f1c0f0'/>
<id>urn:sha1:e6945304187deae0a28ebc65008ec11277f1c0f0</id>
<content type='text'>
The queues represented in queue_bitmap are only CP queues.

Signed-off-by: Yong Zhao &lt;Yong.Zhao@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Extend ROCt to surface UUID for devices that have them</title>
<updated>2020-02-26T19:18:17Z</updated>
<author>
<name>Divya Shikre</name>
<email>DivyaUday.Shikre@amd.com</email>
</author>
<published>2020-02-25T22:17:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0c663695a6cb9820692e7e37239c5be90c77b21d'/>
<id>urn:sha1:0c663695a6cb9820692e7e37239c5be90c77b21d</id>
<content type='text'>
Devices from Arcturus onwards will have their UUID exposed to Thunk.
Adding neccessary functions to the kernel to propagate the uuid.

Signed-off-by: Divya Shikre &lt;DivyaUday.Shikre@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu/gmc_v9: save/restore sdpif regs during S3</title>
<updated>2020-02-25T16:01:26Z</updated>
<author>
<name>Shirish S</name>
<email>shirish.s@amd.com</email>
</author>
<published>2020-01-27T11:05:24Z</published>
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<id>urn:sha1:c2ecd79bec4ecc7f4fa52d91ea9bd3d69e3f54d5</id>
<content type='text'>
fixes S3 issue with IOMMU + S/G  enabled @ 64M VRAM.

Suggested-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Shirish S &lt;shirish.s@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus</title>
<updated>2020-01-30T22:15:27Z</updated>
<author>
<name>Joseph Greathouse</name>
<email>Joseph.Greathouse@amd.com</email>
</author>
<published>2020-01-27T22:08:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=18c6b74e7cfc9a599917d9e98f9835de8208e19a'/>
<id>urn:sha1:18c6b74e7cfc9a599917d9e98f9835de8208e19a</id>
<content type='text'>
In previous gfx9 parts, S_BARRIER shader instructions are implicitly
S_WAITCNT 0 instructions as well. This setting turns off that
mechanism in Arcturus and beyond. With this, shaders must follow the
ISA guide insofar as putting in explicit S_WAITCNT operations even
after an S_BARRIER.

v2: Fix patch title to list component

Signed-off-by: Joseph Greathouse &lt;Joseph.Greathouse@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add EDC counter registers of gc for Arcturus</title>
<updated>2020-01-22T21:36:22Z</updated>
<author>
<name>Dennis Li</name>
<email>Dennis.Li@amd.com</email>
</author>
<published>2020-01-16T04:30:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=19cf0dd4b9d2771015fc9d74ec1b0b9203cf8c5a'/>
<id>urn:sha1:19cf0dd4b9d2771015fc9d74ec1b0b9203cf8c5a</id>
<content type='text'>
add reg headers to gc includes

v2: remove unused registers and fields in this patch set

Signed-off-by: Dennis Li &lt;Dennis.Li@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update mmhub 9.4.1 header files for Acrturus</title>
<updated>2020-01-22T21:35:42Z</updated>
<author>
<name>Dennis Li</name>
<email>Dennis.Li@amd.com</email>
</author>
<published>2020-01-13T08:15:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f519cd13c23e8c884011295b205c1463babbf416'/>
<id>urn:sha1:f519cd13c23e8c884011295b205c1463babbf416</id>
<content type='text'>
Add mask &amp; shift definition of MAM_D(0~3)MEM for all mmhub
ranges.

Signed-off-by: Dennis Li &lt;Dennis.Li@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
