linux/drivers/gpu/drm/amd/include, branch v5.8

drm/amdgpu: add apu flags (v2)

2020-05-22T17:41:53Z

Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: Evan Quan Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/display: Add DC Debug mask to disable features for bringup

2020-05-21T16:37:19Z

[Why] At bringup we want to be able to disable various power features. [How] These features are already exposed as dc_debug_options and exercised on other OSes. Create a new dc_debug_mask module parameter and expose relevant bits, in particular * DC_DISABLE_PIPE_SPLIT * DC_DISABLE_STUTTER * DC_DISABLE_DSC * DC_DISABLE_CLOCK_GATING Signed-off-by: Harry Wentland Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/amdgpu: Add missing GRBM bits for GFX 10.1

2020-05-11T22:03:25Z

Requested bits for UMR support Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/display: move location of dmub_srv.h file

2020-05-05T17:12:33Z

[Why] Make a separation of what belongs in the differen dmub headers dmub_srv.h is for exposing dmub srv interface to rest of driver. other headers inside dmub/inc exposes cmds and definitions that are owned by the firmware [How] keep firmware owned definitions in dmub/inc move stuff that is purely driver interface headers to dmub/ since those are interface calls that are defined for rest of driver to use Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Harry Wentland Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/powerplay: revise the way to retrieve the board parameters

2020-04-22T22:11:45Z

It can support different NV1x ASIC better. And this can guard no member got missing. Signed-off-by: Evan Quan Acked-by: Alex Deucher Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher

drm/amdgpu: retire indirect mmio reg support from cgs

2020-04-09T14:43:18Z

not needed anymore Signed-off-by: Hawking Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

2020-04-01T18:44:43Z

The PWR block was merged into the SMUIO block by revision 12 so we add that to the smuio_12_0_0 headers. (v2): Drop nonsensical smuio_10_0_0 header Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header

2020-04-01T18:44:43Z

The register is part of the PWR block not the GC block. Move to its own header. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/amdgpu: Add missing SMUIO v12 register to headers

2020-04-01T18:44:43Z

This register is needed by umr. Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: cleanup all virtualization detection routine

2020-04-01T18:44:42Z

we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu Reviewed-by: Emily Deng Signed-off-by: Alex Deucher